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authorArnd Bergmann <arnd@arndb.de>2018-03-28 18:15:43 +0300
committerArnd Bergmann <arnd@arndb.de>2018-03-28 18:15:43 +0300
commit3eb8d21ac6c90db1fa8eb440fcdf770e3e815d89 (patch)
tree9908eb6118bdae95352eb25fbcc413032a423f36 /arch/arm/boot
parent77339114bd474b88713cfc18d6a7f3af381863e9 (diff)
parent8dc9b9720380a3c16969932151ba92b558110b2f (diff)
downloadlinux-3eb8d21ac6c90db1fa8eb440fcdf770e3e815d89.tar.xz
Merge tag 'v4.17-rockchip-dts32-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "Rockchip dts32 changes for 4.17" from Heiko Stübner: For general soc-specific changes the rk322x socs got their correct grf compatible set. Other than that there are some board-specific changes like the Rock2 getting its otg port, recovery and power keys enabled. The vyasa board gained an enabled emmc node and the phyCORE boards got UHS speeds in their sd card and a fixed sd-card power supply. Finally the veyron boards dropped a nonstandard and unused property. * tag 'v4.17-rockchip-dts32-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: enable USB-OTG port on Radxa Rock2 Square ARM: dts: rockchip: add recovery button for Rock2 Square ARM: dts: rockchip: add power key for Rock2 Square ARM: dts: rockchip: Add eMMC node for rk3288-vyasa ARM: dts: rockchip: Support UHS mode for SD card on phyCORE-RK3288 RDK ARM: dts: rockchip: Fix supply node for card's power on phycore som ARM: dts: rockchip: add "rockchip,rk3228-grf" compatible for rk322x grf node ARM: dts: rockchip: drop veyron's nonstandard 'backlight-boot-off'
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/rk322x.dtsi2
-rw-r--r--arch/arm/boot/dts/rk3288-phycore-rdk.dts6
-rw-r--r--arch/arm/boot/dts/rk3288-phycore-som.dtsi5
-rw-r--r--arch/arm/boot/dts/rk3288-rock2-som.dtsi4
-rw-r--r--arch/arm/boot/dts/rk3288-rock2-square.dts41
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi1
-rw-r--r--arch/arm/boot/dts/rk3288-vyasa.dts11
7 files changed, 64 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 341deaf62ff6..df1e47858675 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -233,7 +233,7 @@
};
grf: syscon@11000000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
reg = <0x11000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index 1241cbcfc16f..985743fa134c 100644
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -265,7 +265,11 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vdd_io_sd>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 5eae4776ffde..f13bcb1cd3d9 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -336,11 +336,10 @@
regulator-name = "vdd_io_sd";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
+ regulator-off-in-suspend;
};
};
};
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index b9c471fcbd42..51f36a1b698e 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -280,6 +280,10 @@
};
};
+&saradc {
+ vref-supply = <&vcc_18>;
+};
+
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index 0e084b8a86ac..8ccc89dbdfaf 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -39,6 +39,7 @@
*/
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include "rk3288-rock2-som.dtsi"
/ {
@@ -49,6 +50,32 @@
stdout-path = "serial2:115200n8";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+ wakeup-source;
+ };
+ };
+
gpio-leds {
compatible = "gpio-leds";
@@ -220,6 +247,12 @@
};
};
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -261,6 +294,10 @@
};
};
+&saradc {
+ status = "okay";
+};
+
&spdif {
status = "okay";
};
@@ -284,3 +321,7 @@
&usb_host1 {
status = "okay";
};
+
+&usb_otg {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index d752a315f884..be487111d025 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -92,7 +92,6 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
- backlight-boot-off;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index 9842a006e823..14c896bfc639 100644
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -155,6 +155,17 @@
cpu0-supply = <&vdd_cpu>;
};
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ status = "okay";
+};
+
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;