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| author | Beniamino Galvani <b.galvani@gmail.com> | 2014-11-18 17:30:35 +0300 |
|---|---|---|
| committer | Carlo Caione <carlo@caione.org> | 2014-11-18 18:36:14 +0300 |
| commit | 550ab390d7c60b85cd896cf03a34f8eae8a65d69 (patch) | |
| tree | f880749d8051fb56356de52ba330a4194a5c546d /arch/arm/boot/dts | |
| parent | aeff05a39a5a9b9a41fe96ef4f4246cef5fb2f4a (diff) | |
| download | linux-550ab390d7c60b85cd896cf03a34f8eae8a65d69.tar.xz | |
ARM: meson: DTS: enable L2 cache
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/meson.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/meson6.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 4 |
3 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e6539ea5a711..862aae4a3285 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -50,6 +50,13 @@ / { interrupt-parent = <&gic>; + L2: l2-cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@c4301000 { compatible = "arm,cortex-a9-gic"; reg = <0xc4301000 0x1000>, diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 4ba49127779f..8b33be15af94 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -60,12 +60,14 @@ cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x200>; }; cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x201>; }; }; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 42e4026c7ac1..1f442a7fe03b 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -58,24 +58,28 @@ cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x200>; }; cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x201>; }; cpu@202 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x202>; }; cpu@203 { device_type = "cpu"; compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; reg = <0x203>; }; }; |