diff options
| author | Niklas Cassel <niklas.cassel@axis.com> | 2016-10-14 16:09:13 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2016-11-26 02:11:30 +0300 |
| commit | c00f3188417f7071197f9672476d6f28eeaf8835 (patch) | |
| tree | c21ee4ce381c93a2f2e1d3c1029da6735a829959 /arch/arm/boot/dts | |
| parent | 7677796fe69363956730a9cd5262122a0b3d305d (diff) | |
| download | linux-c00f3188417f7071197f9672476d6f28eeaf8835.tar.xz | |
ARM: dts: artpec: add pcie support
Add PCIe support to the ARTPEC-6 SoC. This uses the existing
pcie-artpec6 driver.
So, all that is needed is device tree entries in the DTS.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Jesper Nilsson <jespern@axis.com>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/artpec6-devboard.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/artpec6.dtsi | 29 |
2 files changed, 32 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts index f823ed382ac7..9dfe845694cf 100644 --- a/arch/arm/boot/dts/artpec6-devboard.dts +++ b/arch/arm/boot/dts/artpec6-devboard.dts @@ -46,6 +46,10 @@ status = "okay"; }; +&pcie { + status = "okay"; +}; + ðernet { status = "okay"; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3489019cc0dc..767cbe8d8557 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -67,7 +67,7 @@ }; }; - syscon { + syscon: syscon@f8000000 { compatible = "axis,artpec6-syscon", "syscon"; reg = <0xf8000000 0x48>; }; @@ -154,6 +154,33 @@ interrupt-parent = <&intc>; }; + pcie: pcie@f8050000 { + compatible = "axis,artpec6-pcie", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x2000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* downstream I/O */ + ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + axis,syscon-pcie = <&syscon>; + status = "disabled"; + }; + amba@0 { compatible = "simple-bus"; #address-cells = <0x1>; |