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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2019-10-24 01:13:29 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2019-11-05 13:35:10 +0300 |
| commit | 66e40b3517f7de1b465d4ccc36587cf2ab70a94e (patch) | |
| tree | bf1251b208c316a21787db5b13b2c94abd920616 /arch/arm/boot/dts | |
| parent | ab883313ef625a48704eec3159b43eabe1e5fa38 (diff) | |
| download | linux-66e40b3517f7de1b465d4ccc36587cf2ab70a94e.tar.xz | |
ARM: dts: sunxi: h3/h5: Add MBUS controller node
Both, H3 and H5, contain MBUS, which is the bus used by DMA devices to
access system memory.
MBUS controller is responsible for arbitration between channels based
on set priority and can do some other things as well, like report
bandwidth used. It also maps RAM region to different address than CPU.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 8df29cd05b83..510f83fb234b 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -109,6 +109,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + dma-ranges; ranges; display_clocks: clock@1000000 { @@ -543,6 +544,14 @@ }; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun8i-h3-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 113>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; |