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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-07-20 11:50:44 +0300 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-08-28 17:14:50 +0300 |
| commit | 007a93891dca11dc6f62866ab0c1e25a0db6422c (patch) | |
| tree | 672361cd5e6ba2c1844da71724d0d2ecf8ed8de7 /arch/arm/boot/dts/uniphier-sld8.dtsi | |
| parent | 5b394b2ddf0347bef56e50c69a58773c94343ff3 (diff) | |
| download | linux-007a93891dca11dc6f62866ab0c1e25a0db6422c.tar.xz | |
ARM: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-sld8.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/uniphier-sld8.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index e9b9b4f3c558..dc723bf2f8f2 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -351,7 +351,8 @@ interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; - clocks = <&sys_clk 2>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; resets = <&sys_rst 2>; }; }; |