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authorKishon Vijay Abraham I <kishon@ti.com>2018-02-06 15:58:03 +0300
committerTony Lindgren <tony@atomide.com>2018-03-01 01:27:14 +0300
commit0e43884cca77218d2eccc331396e8cc1f41262a4 (patch)
tree5e5743aa3407888e82c0164baafc6be48e82902f /arch/arm/boot/dts/sun8i-a23-evb.dts
parentf4aa1bd5b4fc80f5f4ecd184caad832fd62c25f7 (diff)
downloadlinux-0e43884cca77218d2eccc331396e8cc1f41262a4.tar.xz
ARM: dts: dra71-evm: Select pull down for mmc1_clk line in default mode
During a short period when the bus voltage is switched from 3.3v to 1.8v, (to enumerate UHS mode), the mmc module is disabled and the mmc IO lines are kept in a state according to the programmed pad mux pull type. According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the host should hold CLK low for at least 5ms. In order to keep the card line low during voltage switch, the pad mux of mmc1_clk line should be configured to pull down. This is specific only to dra71-evm (and not all dra72 based boards) since mmc1_clk line in dra71-evm is not connected to an external pullup. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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