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authorPatrice Chotard <patrice.chotard@st.com>2017-01-06 16:30:21 +0300
committerPatrice Chotard <patrice.chotard@st.com>2017-01-12 19:18:03 +0300
commitb9ec866d223f38eb0bf2a7c836e10031ee17f7af (patch)
tree301f1097dee4e5f6e4a6f91dc13c2adcec27a4e2 /arch/arm/boot/dts/stih410.dtsi
parentb005ebf945e936cacd317a51500cb01033e86aec (diff)
downloadlinux-b9ec866d223f38eb0bf2a7c836e10031ee17f7af.tar.xz
ARM: dts: STiH410-family: fix wrong parent clock frequency
The clock parent was lower than child clock which is not correct. In some use case, it leads to division by zero. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih410.dtsi')
-rw-r--r--arch/arm/boot/dts/stih410.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 8be99d010fb3..3c9672c5b09f 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -131,7 +131,7 @@
<&clk_s_d2_quadfs 0>;
assigned-clock-rates = <297000000>,
- <108000000>,
+ <297000000>,
<0>,
<400000000>,
<400000000>;