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| author | Arnd Bergmann <arnd@arndb.de> | 2023-10-16 16:49:31 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-10-16 16:49:37 +0300 |
| commit | 6fd3e8682b0f1eb46518812353b84afdb8ce29ef (patch) | |
| tree | 5b73d677b48003dd61f38241c528d46604721002 /arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | |
| parent | 68f1d4198cd2860539dc84dd2159f6cb5e88dd94 (diff) | |
| parent | 2138c32af19740ab54bf5622890fe96ba3530b75 (diff) | |
| download | linux-6fd3e8682b0f1eb46518812353b84afdb8ce29ef.tar.xz | |
Merge tag 'qcom-dts-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM DeviceTree updates for v6.7
RPM master stats is introduced for MSM8226 and MSM8974. The PCIe PHY of
SDX55 is transitioned to the new binding. The hall sensor on the Samsung
Galaxy Tab 4 is inverted.
A number of fixes reported from DeviceTree validation are fixed.
* tag 'qcom-dts-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: ipq8064: move keys and leds out of soc node
ARM: dts: qcom: mdm9615: populate vsdcc fixed regulator
ARM: dts: qcom: apq8060: drop incorrect regulator-type
ARM: dts: qcom: apq8064: drop incorrect regulator-type
ARM: dts: qcom: sdx65: fix SDHCI clocks order
ARM: dts: qcom: apq8064: drop label property from DSI
ARM: qcom: msm8974: Add rpm-master-stats node
ARM: qcom: msm8226: Add rpm-master-stats node
ARM: dts: qcom: apq8026-samsung-matisse-wifi: Fix inverted hall sensor
ARM: dts: qcom: drop incorrect cell-index from SPMI
ARM: dts: qcom-sdx55: switch PCIe QMP PHY to new style of bindings
Link: https://lore.kernel.org/r/20231015204558.855987-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/qcom/qcom-sdx55.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 32 |
1 files changed, 12 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 55ce87b75253..2aa5089a8513 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -379,7 +379,7 @@ power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; + phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; @@ -428,7 +428,7 @@ resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; + phys = <&pcie_phy>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -438,18 +438,25 @@ pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; - reg = <0x01c07000 0x1c4>; + reg = <0x01c07000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", - "refgen"; + "refgen", + "pipe"; + + clock-output-names = "pcie_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; @@ -458,20 +465,6 @@ assigned-clock-rates = <100000000>; status = "disabled"; - - pcie_lane: lanes@1c06000 { - reg = <0x01c06000 0x104>, /* tx0 */ - <0x01c06200 0x328>, /* rx0 */ - <0x01c07200 0x1e8>, /* pcs */ - <0x01c06800 0x104>, /* tx1 */ - <0x01c06a00 0x328>, /* rx1 */ - <0x01c07600 0x800>; /* pcs_misc */ - clocks = <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - }; }; ipa: ipa@1e40000 { @@ -645,7 +638,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; tlmm: pinctrl@f100000 { |