diff options
| author | Matthew McClintock <mmcclint@codeaurora.org> | 2018-07-25 11:37:46 +0300 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-09-13 23:37:45 +0300 |
| commit | bcb9ab4c2917e92114d2f4c2b1da97cdf15b471b (patch) | |
| tree | 95b4abe50458c2b543ba3cbd48d596129b0c62a7 /arch/arm/boot/dts/qcom-ipq4019.dtsi | |
| parent | 233c77d4f1d12e4337fba1146d5197f4c0f9107d (diff) | |
| download | linux-bcb9ab4c2917e92114d2f4c2b1da97cdf15b471b.tar.xz | |
ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq support
This adds some operating points for cpu frequeny scaling
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 54 |
1 files changed, 26 insertions, 28 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bbb230b743b2..557fa4bbdded 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -59,14 +59,8 @@ reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - operating-points = < - /* kHz uV (fixed) */ - 48000 1100000 - 200000 1100000 - 500000 1100000 - 716000 1100000 - >; clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@1 { @@ -79,14 +73,8 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - operating-points = < - /* kHz uV (fixed) */ - 48000 1100000 - 200000 1100000 - 500000 1100000 - 666000 1100000 - >; clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@2 { @@ -99,14 +87,8 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - operating-points = < - /* kHz uV (fixed) */ - 48000 1100000 - 200000 1100000 - 500000 1100000 - 666000 1100000 - >; clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { @@ -119,14 +101,8 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - operating-points = < - /* kHz uV (fixed) */ - 48000 1100000 - 200000 1100000 - 500000 1100000 - 666000 1100000 - >; clock-latency = <256000>; + operating-points-v2 = <&cpu0_opp_table>; }; L2: l2-cache { @@ -135,6 +111,28 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-48000000 { + opp-hz = /bits/ 64 <48000000>; + clock-latency-ns = <256000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + clock-latency-ns = <256000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <256000>; + }; + opp-716000000 { + opp-hz = /bits/ 64 <716000000>; + clock-latency-ns = <256000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | |