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authorTony Lindgren <tony@atomide.com>2021-03-10 15:04:31 +0300
committerTony Lindgren <tony@atomide.com>2021-03-10 15:04:31 +0300
commitfbe8285d65a9e7c69fdbe6cc069d33581302c72d (patch)
treeb3a65be80002486cdb257d6fd1669765a8e4cb1b /arch/arm/boot/dts/omap4.dtsi
parente55cc3f0404c6bb22ca843a6d16fae2ca193ca09 (diff)
downloadlinux-fbe8285d65a9e7c69fdbe6cc069d33581302c72d.tar.xz
ARM: dts: Move omap4 mmio-sram out of l3 interconnect
We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap4.dtsi')
-rw-r--r--arch/arm/boot/dts/omap4.dtsi14
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 5fe4dcaa24c5..d0c809715444 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -58,6 +58,15 @@
};
};
+ /*
+ * Needed early by omap4_sram_init() for barrier, do not move to l3
+ * interconnect as simple-pm-bus probes at module_init() time.
+ */
+ ocmcram: sram@40304000 {
+ compatible = "mmio-sram";
+ reg = <0x40304000 0xa000>; /* 40k */
+ };
+
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
@@ -136,11 +145,6 @@
l4_abe: interconnect@40100000 {
};
- ocmcram: sram@40304000 {
- compatible = "mmio-sram";
- reg = <0x40304000 0xa000>; /* 40k */
- };
-
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,