diff options
| author | James Liao <jamesjj.liao@mediatek.com> | 2016-11-04 10:43:07 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2016-11-11 17:25:03 +0300 |
| commit | adf6eb7774a90bd75e1284710d5a83cd7b707228 (patch) | |
| tree | f2d5b8e059ad02572302998e50aa5a6535884f95 /arch/arm/boot/dts/mt2701.dtsi | |
| parent | a3207d644fb89e5d7d5e01f00c04dcfc6d2d44d5 (diff) | |
| download | linux-adf6eb7774a90bd75e1284710d5a83cd7b707228.tar.xz | |
arm: dts: mt2701: Add clock controller device nodes
Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg and apmixedsys. This patch also add two oscillators that
provide clocks for MT2701.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/mt2701.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/mt2701.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 18596a2c58a1..c9a8dbf415ff 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -12,8 +12,10 @@ * GNU General Public License for more details. */ +#include <dt-bindings/clock/mt2701-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/mt2701-resets.h> #include "skeleton64.dtsi" #include "mt2701-pinfunc.h" @@ -77,6 +79,20 @@ #clock-cells = <0>; }; + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + rtc32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "rtc32k"; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; @@ -104,6 +120,26 @@ reg = <0 0x10005000 0 0x1000>; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt2701-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2701-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2701-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; @@ -128,6 +164,12 @@ reg = <0 0x10200100 0 0x1c>; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2701-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10211000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; |