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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-04-22 13:45:02 +0300
committerKevin Hilman <khilman@baylibre.com>2018-04-27 22:07:55 +0300
commite8d85d767956455060ec016cf8fef2d58c24ad14 (patch)
tree136200dad9a5ce4db667848e163019a9c781e69b /arch/arm/boot/dts/meson8b.dtsi
parent17b66027e6a55af250d754d4bbb997d37162dee7 (diff)
downloadlinux-e8d85d767956455060ec016cf8fef2d58c24ad14.tar.xz
ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU
Enable the performance monitor unit on Meson8b. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8b.dtsi')
-rw-r--r--arch/arm/boot/dts/meson8b.dtsi17
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 553b82174604..6cfd7e225cee 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -55,7 +55,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@200 {
+ cpu0: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -64,7 +64,7 @@
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
- cpu@201 {
+ cpu1: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -73,7 +73,7 @@
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
- cpu@202 {
+ cpu2: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -82,7 +82,7 @@
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
- cpu@203 {
+ cpu3: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
@@ -92,6 +92,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a5-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;