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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-11-16 23:42:34 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2018-11-29 03:49:03 +0300 |
| commit | 523b8b31d3e1292b69f233e1a1814151878d6ac8 (patch) | |
| tree | 0eb5b752f7353fc4687e7ed7ebfd7006959b7019 /arch/arm/boot/dts/meson.dtsi | |
| parent | 7e26335b1a3fb2400fcf6d5eb35328257ea2e139 (diff) | |
| download | linux-523b8b31d3e1292b69f233e1a1814151878d6ac8.tar.xz | |
ARM: dts: meson: add the TIMER B/C/D interrupts
The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events.
For each of these a separate interrupt exists.
Pass these interrupts to allow using the timers other than TIMER A.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/meson.dtsi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 0d9faf1a51ea..f0255450bcb2 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -200,7 +200,10 @@ timer@9940 { compatible = "amlogic,meson6-timer"; reg = <0x9940 0x18>; - interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; }; }; |