diff options
| author | Josua Mayer <josua@solid-run.com> | 2024-01-04 20:48:09 +0300 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2024-02-27 19:20:14 +0300 |
| commit | 0d390855f61b03db829783311a175b272d0ebc17 (patch) | |
| tree | 8363edc40754174689d881ca6b8aed4425db9c4f /arch/arm/boot/dts/marvell | |
| parent | d265e1fecf4fdbf2aa46d278bc370890d8e7c707 (diff) | |
| download | linux-0d390855f61b03db829783311a175b272d0ebc17.tar.xz | |
arm: dts: marvell: clearfog-gtr: add missing pinctrl for all used gpios
Various control signals such as sfp module-absence, pci-e reset or led
gpios were missing pinctrl nodes, leaving any u-boot choices in place.
Since U-Boot is shared between multiple board variants, i.e. a388
clearfog pro / base, clearfog gtr l8 / s4, it is better to explicitly
configure functions.
Add explicit pinctrl entries for all gpios currently in use.
Additionally the loss-of-signal gpio specified is invalid, in fact los
only has a pull-up on the board but no gpio connection to the cpu.
Remove this stray reference.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/marvell')
| -rw-r--r-- | arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi | 42 |
1 files changed, 39 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index 8eabb60765b0..39ac97edb463 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -162,6 +162,22 @@ marvell,function = "gpio"; }; + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35", "mpp44"; + marvell,function = "gpio"; + }; + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { marvell,pins = "mpp48"; marvell,function = "gpio"; @@ -179,6 +195,12 @@ marvell,function = "sd0"; }; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1"; @@ -193,6 +215,11 @@ marvell,pins = "mpp22"; marvell,function = "gpio"; }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; + marvell,function = "gpio"; + }; }; sdhci@d8000 { @@ -221,21 +248,26 @@ }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ + /* CON3 - serdes 0 */ pcie@1,0 { reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON4 - serdes 2 */ pcie@2,0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON2 - serdes 4 */ pcie@3,0 { reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -243,10 +275,12 @@ }; }; + /* CON5 */ sfp0: sfp { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; @@ -273,6 +307,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; @@ -408,7 +444,7 @@ }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable { @@ -420,7 +456,7 @@ }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { |