diff options
| author | Roland Stigge <stigge@antcom.de> | 2012-06-14 18:16:18 +0400 |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-06-14 18:16:18 +0400 |
| commit | ac5ced91aa6b5013027d3313824c9c5afb071f23 (patch) | |
| tree | 667e75cbeab6c30f8bffd8e72d42501506926239 /arch/arm/boot/dts/lpc32xx.dtsi | |
| parent | c70426f1534a7d8e52e478ce67fd4634cc588741 (diff) | |
| download | linux-ac5ced91aa6b5013027d3313824c9c5afb071f23.tar.xz | |
ARM: LPC32xx: High Speed UART configuration via DT
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
configuration. On the PHY3250 reference board, UART2 is enabled.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/lpc32xx.dtsi | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index acb68171d04d..34a73f34621c 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -212,18 +212,24 @@ }; uart1: serial@40014000 { - compatible = "nxp,serial"; + compatible = "nxp,lpc3220-hsuart"; reg = <0x40014000 0x1000>; + interrupts = <26 0>; + status = "disabled"; }; uart2: serial@40018000 { - compatible = "nxp,serial"; + compatible = "nxp,lpc3220-hsuart"; reg = <0x40018000 0x1000>; + interrupts = <25 0>; + status = "disabled"; }; - uart7: serial@4001C000 { - compatible = "nxp,serial"; - reg = <0x4001C000 0x1000>; + uart7: serial@4001c000 { + compatible = "nxp,lpc3220-hsuart"; + reg = <0x4001c000 0x1000>; + interrupts = <24 0>; + status = "disabled"; }; rtc@40024000 { |