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| author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-04-30 16:56:34 +0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-05-05 04:52:28 +0400 |
| commit | 327e154289772870476b3787f125fc9618f81c7a (patch) | |
| tree | f3b5f16dc13be98aa0a6b0d0163760ebeeacff83 /arch/arm/boot/dts/kirkwood.dtsi | |
| parent | 2ab516adb3489347331a89070a37eaf1907679d8 (diff) | |
| download | linux-327e154289772870476b3787f125fc9618f81c7a.tar.xz | |
ARM: dts: kirkwood: consolidate common pinctrl settings
All SoCs have the same pinctrl setting for NAND, UART0/1, SPI, TWSI0,
and GBE1. Move it to the common pinctrl node that we now have.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1398862602-29595-8-git-send-email-sebastian.hesselbarth@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/kirkwood.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/kirkwood.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 028003e12111..5d412e71b9fb 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -74,6 +74,39 @@ pinctrl: pin-controller@10000 { /* set compatible property in SoC file */ reg = <0x10000 0x20>; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", "mpp27", + "mpp30", "mpp31", "mpp32", "mpp33"; + marvell,function = "ge1"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", "mpp19"; + marvell,function = "nand"; + }; + + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; }; core_clk: core-clocks@10030 { |