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| author | Fabio Estevam <festevam@gmail.com> | 2020-07-13 16:04:16 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-07-20 05:19:30 +0300 |
| commit | cfe7d1bd1122a3860ac4f3256c6e8fcba3ae9a2f (patch) | |
| tree | ba0063f9d28a06dd06c77dd0b5aafd1141cb0e9f /arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |
| parent | 91ea910809953beb95246bc3c933bd4e1bffdf59 (diff) | |
| download | linux-cfe7d1bd1122a3860ac4f3256c6e8fcba3ae9a2f.tar.xz | |
ARM: dts: imx6qdl-sabresd: Pass reset-assert-us
According to the AR8031 datasheet:
"When using crystal, clock is generated internally after the power is
stable. In order to get reliable power-on-reset, it is recommended to
keep asserting the reset low signal long enough (10 ms) to ensure the
clock is stable and clock-to-reset (1 ms) requirement is satisfied."
Pass the 'reset-assert-us' property to describe such requirement.
While at it, use the 'reset-gpios' property inside the the mdio
node instead of the deprecated usage of 'phy-reset-gpios'.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Soeren Moch <smoch@web.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabresd.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index eaa2146bb937..68b3e68cb8df 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -204,7 +204,6 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-handle = <&phy>; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; fsl,magic-packet; status = "okay"; @@ -215,6 +214,8 @@ phy: ethernet-phy@1 { reg = <1>; qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; |