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authorShawn Guo <shawn.guo@linaro.org>2012-08-11 06:47:14 +0400
committerShawn Guo <shawn.guo@linaro.org>2012-09-11 12:26:46 +0400
commit99d5f0cc17c0c7191e1bb9dc40849a1711a77439 (patch)
tree76637133a9108e44e221d617c4aae69becee3b51 /arch/arm/boot/dts/imx6q-sabrelite.dts
parent52ccd4920301b9fecbac577ad4283995730ecf76 (diff)
downloadlinux-99d5f0cc17c0c7191e1bb9dc40849a1711a77439.tar.xz
ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and enet
Add missing pinctrl of usdhc and enet for imx6q-sabrelite board. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-sabrelite.dts')
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index dc1933c73067..e34ace784ea3 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -51,8 +51,13 @@
gpios {
pinctrl_gpio_hog: gpiohog {
fsl,pins = <
- 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+ 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+ 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+ 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+ 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+ 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+ 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
};
@@ -71,12 +76,16 @@
};
ethernet@02188000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
@@ -84,6 +93,8 @@
};
usdhc@0219c000 { /* uSDHC4 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;