diff options
| author | Viresh Kumar <viresh.kumar@linaro.org> | 2018-11-16 13:01:10 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2018-11-18 17:17:08 +0300 |
| commit | 670734f5581023a2e695e82ea662e4d603fd3e8a (patch) | |
| tree | d7c91412ccf452f6ecb0f8e1e7109b5b1fab6607 /arch/arm/boot/dts/exynos5422-odroidhc1.dts | |
| parent | 6e2422ff9492514a618746f490ff816d65c68f3b (diff) | |
| download | linux-670734f5581023a2e695e82ea662e4d603fd3e8a.tar.xz | |
ARM: dts: exynos: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5422-odroidhc1.dts')
| -rw-r--r-- | arch/arm/boot/dts/exynos5422-odroidhc1.dts | 106 |
1 files changed, 65 insertions, 41 deletions
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 8f332be143f7..d271e7548826 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -56,24 +56,30 @@ */ map0 { trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>; - }; - map1 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu4 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; /* * When reaching cpu0_alert1, reduce CPU * further, down to 600 MHz (12 steps for big, * 7 steps for LITTLE). */ - map2 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { + map1 { trip = <&cpu0_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -99,19 +105,25 @@ cooling-maps { map0 { trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map1 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu4 0 2>; - }; - map2 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { trip = <&cpu1_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -137,19 +149,25 @@ cooling-maps { map0 { trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map1 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu4 0 2>; - }; - map2 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { trip = <&cpu2_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -175,19 +193,25 @@ cooling-maps { map0 { trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map1 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu4 0 2>; - }; - map2 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { trip = <&cpu3_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; |