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author | Olof Johansson <olof@lixom.net> | 2019-10-22 00:38:03 +0300 |
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committer | Olof Johansson <olof@lixom.net> | 2019-10-22 00:38:04 +0300 |
commit | 5d8b20c131dd51e3635f0afe419397a9789cc058 (patch) | |
tree | cb73fbc9e34b36da5949fea3c4a3754a55a7d2d2 /arch/arm/boot/dts/exynos5420.dtsi | |
parent | 16adb5ce3b2bfdbd039eb4f08ae06382543da616 (diff) | |
parent | 41f277be1d028e64fb8d5e91a7ce74df600bde54 (diff) | |
download | linux-5d8b20c131dd51e3635f0afe419397a9789cc058.tar.xz |
Merge tag 'samsung-dt-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS changes for DMC driver for v5.5
Add bindings and update device tree sources of Exynos5422 platforms with
new Dynamic Memory Controller nodes and properties.
* tag 'samsung-dt-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
dt-bindings: memory-controllers: exynos5422-dmc: Correct example syntax and memory region
ARM: dts: exynos: Add interrupts to DMC controller in Exynos5422
ARM: dts: exynos: Extend mapped region for DMC on Exynos5422
dt-bindings: memory-controllers: exynos5422-dmc: Add interrupt mode
dt-bindings: ddr: Add bindings for Samsung LPDDR3 memories
ARM: dts: exynos: Add DMC device to Exynos5422 and Odroid XU3-family boards
ARM: dts: exynos: Add syscon compatible to clock controller on Exynos542x
dt-bindings: memory-controllers: Add Exynos5422 DMC device description
dt-bindings: ddr: Add bindings for LPDDR3 memories
dt-bindings: ddr: Rename lpddr2 directory
Link: https://lore.kernel.org/r/20191021180453.29455-6-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
-rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 76 |
1 files changed, 75 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2c131ad78c09..d39907a41f78 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -175,7 +175,7 @@ }; clock: clock-controller@10010000 { - compatible = "samsung,exynos5420-clock"; + compatible = "samsung,exynos5420-clock", "syscon"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; @@ -237,6 +237,32 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>, <16 1>; + interrupt-names = "drex_0", "drex_1"; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MCLK_CDREX>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mclk_cdrex"; + samsung,syscon-clk = <&clock>; + status = "disabled"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -273,6 +299,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d60000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; |