diff options
| author | Kamil Debski <k.debski@samsung.com> | 2014-05-22 02:50:48 +0400 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2014-05-22 02:52:30 +0400 |
| commit | dba2f05880c5bdcd6fbd8273404695ee4cd41385 (patch) | |
| tree | 26bdc786af94359c21ac8da531f25cc0ec36ae95 /arch/arm/boot/dts/exynos5250.dtsi | |
| parent | dfbbdbf4405d73012f158ae39dc3dd66cebcf418 (diff) | |
| download | linux-dba2f05880c5bdcd6fbd8273404695ee4cd41385.tar.xz | |
ARM: dts: Add usb2phy to exynos5250
Add support to PHY of USB2 of the Exynos5250 SoC.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[gautam.vivek@samsung.com: Split the usb phy entries]
[gautam.vivek@samsung.com: Added phy entry for OHCI also along with EHCI]
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5250.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos5250.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 8e9b9a31d959..cb296429b3ec 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -577,6 +577,12 @@ clocks = <&clock CLK_USB2>; clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy_gen 1>; + }; }; usb@12120000 { @@ -586,6 +592,12 @@ clocks = <&clock CLK_USB2>; clock-names = "usbhost"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&usb2_phy_gen 1>; + }; }; usb2_phy: usbphy@12130000 { @@ -603,6 +615,16 @@ }; }; + usb2_phy_gen: phy@12130000 { + compatible = "samsung,exynos5250-usb2-phy"; + reg = <0x12130000 0x100>; + clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + samsung,pmureg-phandle = <&pmu_system_controller>; + }; + pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; reg = <0x12dd0000 0x100>; |