diff options
| author | Tero Kristo <t-kristo@ti.com> | 2018-11-28 13:45:07 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-11-29 22:08:23 +0300 |
| commit | b79e7b3bd1f2b66186278e8df80f371f310138f1 (patch) | |
| tree | 206bbac712058b4ac2236dfb3cf02ea71ca21ab2 /arch/arm/boot/dts/dra7-l4.dtsi | |
| parent | 5d2632a577baa735ad05ec745a2f95997d5ad9e0 (diff) | |
| download | linux-b79e7b3bd1f2b66186278e8df80f371f310138f1.tar.xz | |
ARM: dts: dra7: Move the ti,no-idle quirk on proper gmac node
Hwmod parses the DT hierarchically from root to search for matching
ti,hwmod property. With the introduction of L4 data, we have two nodes
with the ti,hwmod = "gmac" declaration, and the hwmod core only matches
the first one found, which is the target-module one. This node incorrectly
dropped the ti,no-idle flag, which causes number of problems, like ignoring
errata i877, and also causing an intermittent boot failure on certain dra7
boards.
Fix the issue by moving the ti,no-idle flag to the proper node.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7-l4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7-l4.dtsi | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 7e5c0d4f438e..6c01ada9197a 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3021,6 +3021,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x84000 0x4000>; + /* + * Do not allow gating of cpsw clock as workaround + * for errata i877. Keeping internal clock disabled + * causes the device switching characteristics + * to degrade over time and eventually fail to meet + * the data manual delay time/skew specs. + */ + ti,no-idle; mac: ethernet@0 { compatible = "ti,dra7-cpsw","ti,cpsw"; @@ -3040,15 +3048,6 @@ #size-cells = <1>; /* - * Do not allow gating of cpsw clock as workaround - * for errata i877. Keeping internal clock disabled - * causes the device switching characteristics - * to degrade over time and eventually fail to meet - * the data manual delay time/skew specs. - */ - ti,no-idle; - - /* * rx_thresh_pend * rx_pend * tx_pend |