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authorAndrew Jeffery <andrew@aj.id.au>2019-07-12 06:37:25 +0300
committerJoel Stanley <joel@jms.id.au>2019-08-21 06:58:38 +0300
commitc35227958d7ecceae42a7d958380eae906f7b8e6 (patch)
tree7b29adc484fd7000ab209397120677b431bce24f /arch/arm/boot/dts/aspeed-g5.dtsi
parent0a1dcf954ece215284e2a7765613c559d20590fc (diff)
downloadlinux-c35227958d7ecceae42a7d958380eae906f7b8e6.tar.xz
ARM: dts: aspeed: Describe SD controllers
The AST2400 and AST2500 both share the same SD controller, at the same location in the physical address space and the same hardware interrupt, with the same clock configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g5.dtsi')
-rw-r--r--arch/arm/boot/dts/aspeed-g5.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index ca36d18d41f4..f360b6c565a5 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -267,6 +267,34 @@
reg = <0x1e720000 0x9000>; // 36K
};
+ sdmmc: sd-controller@1e740000 {
+ compatible = "aspeed,ast2500-sd-controller";
+ reg = <0x1e740000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e740000 0x10000>;
+ clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
+ status = "disabled";
+
+ sdhci0: sdhci@100 {
+ compatible = "aspeed,ast2500-sdhci";
+ reg = <0x100 0x100>;
+ interrupts = <26>;
+ sdhci,auto-cmd12;
+ clocks = <&syscon ASPEED_CLK_SDIO>;
+ status = "disabled";
+ };
+
+ sdhci1: sdhci@200 {
+ compatible = "aspeed,ast2500-sdhci";
+ reg = <0x200 0x100>;
+ interrupts = <26>;
+ sdhci,auto-cmd12;
+ clocks = <&syscon ASPEED_CLK_SDIO>;
+ status = "disabled";
+ };
+ };
+
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;