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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-05-07 16:19:53 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-05-14 17:40:38 +0300 |
| commit | 45e75c425bdd1dd75d93eeaaef4c81d1563f2efa (patch) | |
| tree | 3dc9b97357886feae7aacdb65c4da12a096f8729 /arch/arm/boot/dts/aspeed-g5.dtsi | |
| parent | 2acb79e15119512da9b6a49906840e7678cfb618 (diff) | |
| download | linux-45e75c425bdd1dd75d93eeaaef4c81d1563f2efa.tar.xz | |
ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts
R-Mobile APE6 (r8a73a4) contains four Cortex-A15 and four Cortex-A7
cores, hence the second interrupt specifier cell for Private Peripheral
Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", so GIC interrupts are
delivered to all 8 processor cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g5.dtsi')
0 files changed, 0 insertions, 0 deletions