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| author | Joel Stanley <joel@jms.id.au> | 2020-09-21 12:16:44 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2020-09-25 03:44:12 +0300 |
| commit | fe100b382c1c052b63c14091fd8bb3fe932453ae (patch) | |
| tree | abac7568839e6322448b4ae8b053e003fafc0623 /arch/arm/boot/dts/aspeed-g4.dtsi | |
| parent | e0218dca5787c851b403fcbc33cdfec795446fca (diff) | |
| download | linux-fe100b382c1c052b63c14091fd8bb3fe932453ae.tar.xz | |
ARM: dts: aspeed: Add silicon id node
This register describes the silicon id and chip unique id. It varies
between CPU revisions, but is always part of the SCU.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200921091644.133107-4-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-g4.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 82f0213e3a3c..b3dafbc8caca 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -192,6 +192,11 @@ status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>; + }; + pinctrl: pinctrl@80 { reg = <0x80 0x18>, <0xa0 0x10>; compatible = "aspeed,ast2400-pinctrl"; |