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| author | Cédric Le Goater <clg@kaod.org> | 2017-03-01 17:26:42 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2017-03-06 02:08:26 +0300 |
| commit | 74dc3cd32e062b664e78c2e61331b4e0caac7822 (patch) | |
| tree | cddf7661d73ae05ddfa98dad00d8c633b3fa7962 /arch/arm/boot/dts/aspeed-g4.dtsi | |
| parent | c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 (diff) | |
| download | linux-74dc3cd32e062b664e78c2e61331b4e0caac7822.tar.xz | |
ARM: dts: aspeed: add SPI controller bindings
Let's define the SPI controllers in the Aspeed SoCs AST2500 and
AST2400 and also enable these, as well as the chips, on the associated
platforms.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-g4.dtsi | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 0b4932cc02a8..7ef6442d0ade 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -33,6 +33,35 @@ #size-cells = <1>; ranges; + fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0x94 + 0x20000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-fmc"; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi: flash-controller@1e630000 { + reg = < 0x1e630000 0x18 + 0x30000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; |