diff options
| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2013-04-12 18:29:08 +0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-04-15 19:00:21 +0400 |
| commit | 82a682676ce34e59369f60168a8729348aaae4d0 (patch) | |
| tree | 4981ab52ed82202ccf6b2bce1e2d80dabaf2cc95 /arch/arm/boot/dts/armada-xp-mv78230.dtsi | |
| parent | b18ea4dc7746f1270bbe3a0817f9a034eec031a8 (diff) | |
| download | linux-82a682676ce34e59369f60168a8729348aaae4d0.tar.xz | |
ARM: dts: mvebu: Convert all the mvebu files to use the range property
This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-mv78230.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-mv78230.dtsi | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index e072a53dc9b0..12905abf4ca3 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -46,7 +46,7 @@ soc { pinctrl { compatible = "marvell,mv78230-pinctrl"; - reg = <0xd0018000 0x38>; + reg = <0x18000 0x38>; sdio_pins: sdio-pins { marvell,pins = "mpp30", "mpp31", "mpp32", @@ -55,9 +55,9 @@ }; }; - gpio0: gpio@d0018100 { + gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; - reg = <0xd0018100 0x40>; + reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; #gpio-cells = <2>; @@ -66,9 +66,9 @@ interrupts = <82>, <83>, <84>, <85>; }; - gpio1: gpio@d0018140 { + gpio1: gpio@18140 { compatible = "marvell,orion-gpio"; - reg = <0xd0018140 0x40>; + reg = <0x18140 0x40>; ngpios = <17>; gpio-controller; #gpio-cells = <2>; @@ -92,17 +92,17 @@ bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ - 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ - 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ - 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ - 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ + ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ + 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ + 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ + 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ pcie@1,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -118,7 +118,7 @@ pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>; + assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -134,7 +134,7 @@ pcie@3,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>; + assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -150,7 +150,7 @@ pcie@4,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>; + assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -166,7 +166,7 @@ pcie@9,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>; + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; |