diff options
| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2014-02-20 15:11:31 +0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-02-22 08:11:03 +0400 |
| commit | d11548e3113961b3d3c0b362f0dbe72d72a7959b (patch) | |
| tree | a838d5d85714ed706b0b6569635b739b77e64ca3 /arch/arm/boot/dts/armada-38x.dtsi | |
| parent | f327d43da130fe6a4a0b3ecf6ad27eff7fd92877 (diff) | |
| download | linux-d11548e3113961b3d3c0b362f0dbe72d72a7959b.tar.xz | |
ARM: mvebu: use macros for interrupt flags on Armada 375/38x
Instead of hardcoding the values of the interrupt flags, use the
macros provided by <include/dt-bindings/interrupt-controller/irq.h>
and <include/dt-bindings/interrupt-controller/arm-gic.h> for the
Armada 375 and Armada 38x Device Tree files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-38x.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 45 |
1 files changed, 25 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 502d21ae7b61..812ce280b349 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -14,6 +14,7 @@ #include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -110,7 +111,7 @@ timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; - interrupts = <GIC_PPI 13 0x301>; + interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; clocks = <&coreclk 2>; }; @@ -129,7 +130,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <0>; - interrupts = <GIC_SPI 1 0x4>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -140,7 +141,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; - interrupts = <GIC_SPI 63 0x4>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -150,7 +151,7 @@ reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 2 0x4>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -161,7 +162,7 @@ reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 3 0x4>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; @@ -171,7 +172,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; - interrupts = <GIC_SPI 12 4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; status = "disabled"; }; @@ -180,7 +181,7 @@ compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; - interrupts = <GIC_SPI 13 4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <1>; status = "disabled"; }; @@ -198,8 +199,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <GIC_SPI 53 0x4>, <GIC_SPI 54 0x4>, - <GIC_SPI 55 0x4>, <GIC_SPI 56 0x4>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; }; gpio1: gpio@18140 { @@ -210,8 +213,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <GIC_SPI 58 0x4>, <GIC_SPI 59 0x4>, - <GIC_SPI 60 0x4>, <GIC_SPI 61 0x4>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; }; system-controller@18200 { @@ -245,17 +250,17 @@ #size-cells = <1>; interrupt-controller; msi-controller; - interrupts = <GIC_PPI 15 0x4>; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; }; timer@20300 { compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; - interrupts-extended = <&gic GIC_SPI 8 4>, - <&gic GIC_SPI 9 4>, - <&gic GIC_SPI 10 4>, - <&gic GIC_SPI 11 4>, + interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; clocks = <&coreclk 2>, <&refclk>; @@ -286,12 +291,12 @@ status = "okay"; xor00 { - interrupts = <GIC_SPI 22 0x4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; dmacap,memcpy; dmacap,xor; }; xor01 { - interrupts = <GIC_SPI 23 0x4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; dmacap,memcpy; dmacap,xor; dmacap,memset; @@ -306,12 +311,12 @@ status = "okay"; xor10 { - interrupts = <GIC_SPI 65 0x4>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; dmacap,memcpy; dmacap,xor; }; xor11 { - interrupts = <GIC_SPI 66 0x4>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; dmacap,memcpy; dmacap,xor; dmacap,memset; |