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| author | Bo Yan <byan@nvidia.com> | 2015-03-31 23:30:48 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-04-01 13:12:03 +0300 |
| commit | 6d1966dfd6e0ad2f8aa4b664ae1a62e33abe1998 (patch) | |
| tree | 3b3614dd3e76d608abb56fa9bf781c437f18b66b /arch/arm/boot/dts/am437x-gp-evm.dts | |
| parent | 905e8c5dcaa147163672b06fe9dcb5abaacbc711 (diff) | |
| download | linux-6d1966dfd6e0ad2f8aa4b664ae1a62e33abe1998.tar.xz | |
arm64: fix midr range for Cortex-A57 erratum 832075
Register MIDR_EL1 is masked to get variant and revision fields, then
compared against midr_range_min and midr_range_max when checking
whether CPU is affected by any particular erratum. However, variant
and revision fields in MIDR_EL1 are separated by 16 bits, so the min
and max of midr range should be constructed accordingly, otherwise
the patch will not be applied when variant field is non-0.
Cc: stable@vger.kernel.org # 3.19+
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Bo Yan <byan@nvidia.com>
[will: use MIDR_VARIANT_SHIFT to construct upper bound]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/boot/dts/am437x-gp-evm.dts')
0 files changed, 0 insertions, 0 deletions