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| author | Masanari Iida <standby24x7@gmail.com> | 2013-03-16 15:53:05 +0400 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2013-03-18 17:57:53 +0400 |
| commit | cf2fbdd26f80046725a11a80683a03baf27fae82 (patch) | |
| tree | 159d41ee54caf37e52835c072b835df57a0a235f /arch/arc/plat-arcfpga | |
| parent | ce03cb20640b94d6124decec36db4d84ee30c83c (diff) | |
| download | linux-cf2fbdd26f80046725a11a80683a03baf27fae82.tar.xz | |
treewide: Fix typos in printk and comment
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/arc/plat-arcfpga')
| -rw-r--r-- | arch/arc/plat-arcfpga/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig index b41e786cdbc0..295cefeb25d3 100644 --- a/arch/arc/plat-arcfpga/Kconfig +++ b/arch/arc/plat-arcfpga/Kconfig @@ -53,7 +53,7 @@ menuconfig ARC_HAS_BVCI_LAT_UNIT bool "BVCI Bus Latency Unit" depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4 help - IP to add artifical latency to BVCI Bus Based FPGA builds. + IP to add artificial latency to BVCI Bus Based FPGA builds. The default latency (even worst case) for FPGA is non-realistic (~10 SDRAM, ~5 SSRAM). |