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| author | Vineet Gupta <vgupta@synopsys.com> | 2013-01-18 13:42:19 +0400 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-02-15 21:45:50 +0400 |
| commit | 95d6976d20a25fa1684f849f26cd3387b5ba7150 (patch) | |
| tree | f3cd6472578c66dafdc13a791c4ca5d100a9d45c /arch/arc/include/asm/arcregs.h | |
| parent | 55bb9480f9159b229ac3c3454c97b62d1e0a7e80 (diff) | |
| download | linux-95d6976d20a25fa1684f849f26cd3387b5ba7150.tar.xz | |
ARC: Cache Flush Management
* ARC700 has VIPT L1 Caches
* Caches don't snoop and are not coherent
* Given the PAGE_SIZE and Cache associativity, we don't support aliasing
D$ configurations (yet), but do allow aliasing I$ configs
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/arcregs.h')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 5131bb3d4fcd..c6e28053fb70 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -58,6 +58,33 @@ #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ +/* Instruction cache related Auxiliary registers */ +#define ARC_REG_IC_BCR 0x77 /* Build Config reg */ +#define ARC_REG_IC_IVIC 0x10 +#define ARC_REG_IC_CTRL 0x11 +#define ARC_REG_IC_IVIL 0x19 +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_REG_IC_PTAG 0x1E +#endif + +/* Bit val in IC_CTRL */ +#define IC_CTRL_CACHE_DISABLE 0x1 + +/* Data cache related Auxiliary registers */ +#define ARC_REG_DC_BCR 0x72 +#define ARC_REG_DC_IVDC 0x47 +#define ARC_REG_DC_CTRL 0x48 +#define ARC_REG_DC_IVDL 0x4A +#define ARC_REG_DC_FLSH 0x4B +#define ARC_REG_DC_FLDL 0x4C +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_REG_DC_PTAG 0x5C +#endif + +/* Bit val in DC_CTRL */ +#define DC_CTRL_INV_MODE_FLUSH 0x40 +#define DC_CTRL_FLUSH_STATUS 0x100 + /* * Floating Pt Registers * Status regs are read-only (build-time) so need not be saved/restored @@ -132,6 +159,31 @@ #endif +#define READ_BCR(reg, into) \ +{ \ + unsigned int tmp; \ + tmp = read_aux_reg(reg); \ + if (sizeof(tmp) == sizeof(into)) { \ + into = *((typeof(into) *)&tmp); \ + } else { \ + extern void bogus_undefined(void); \ + bogus_undefined(); \ + } \ +} + +#define WRITE_BCR(reg, into) \ +{ \ + unsigned int tmp; \ + if (sizeof(tmp) == sizeof(into)) { \ + tmp = (*(unsigned int *)(into)); \ + write_aux_reg(reg, tmp); \ + } else { \ + extern void bogus_undefined(void); \ + bogus_undefined(); \ + } \ +} + + #ifdef CONFIG_ARC_FPU_SAVE_RESTORE /* These DPFP regs need to be saved/restored across ctx-sw */ struct arc_fpu { @@ -141,6 +193,34 @@ struct arc_fpu { }; #endif +/* + *************************************************************** + * Build Configuration Registers, with encoded hardware config + */ + +struct bcr_cache { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; +#else + unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; +#endif +}; + +/* + ******************************************************************* + * Generic structures to hold build configuration used at runtime + */ + +struct cpuinfo_arc_cache { + unsigned int has_aliasing, sz, line_len, assoc, ver; +}; + +struct cpuinfo_arc { + struct cpuinfo_arc_cache icache, dcache; +}; + +extern struct cpuinfo_arc cpuinfo_arc700[]; + #endif /* __ASEMBLY__ */ #endif /* __KERNEL__ */ |