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author | Bjorn Helgaas <bhelgaas@google.com> | 2024-09-19 22:25:30 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-09-19 22:25:30 +0300 |
commit | d1624da381cb1d9c877e631ec07ee10cb3664bbb (patch) | |
tree | 962a1651dff50072063272afe26ad14c40bd4af2 /Documentation | |
parent | f8ca62bff229d5afbbfe275d0931357a9ec04f55 (diff) | |
parent | c538d40f365b5b6d7433d371710f58e8b266fb19 (diff) | |
download | linux-d1624da381cb1d9c877e631ec07ee10cb3664bbb.tar.xz |
Merge branch 'pci/controller/j721e'
- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the
ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli)
- Extract the cadence link setup from cdns_pcie_host_setup() so link setup
can be done separately during resume (Thomas Richard)
- Use dev_err_probe() to simplify j721e probe (Thomas Richard)
- Add T_PERST_CLK_US definition for the mandatory delay between Refclk
becoming stable and PERST# being deasserted (Thomas Richard)
- Add j721e suspend and resume support (Théo Lebrun)
* pci/controller/j721e:
PCI: j721e: Add suspend and resume support
PCI: j721e: Use T_PERST_CLK_US macro
PCI: Add T_PERST_CLK_US macro
PCI: j721e: Add reset GPIO to struct j721e_pcie
PCI: j721e: Use dev_err_probe() in the probe() function
PCI: cadence: Set cdns_pcie_host_init() global
PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists
dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 15a2658ceeef..69b499c96c71 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -38,6 +38,16 @@ properties: - const: reg - const: cfg + ti,syscon-acspcie-proxy-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the ACSPCIE Proxy Control Register + - description: Bitmask corresponding to the PAD IO Buffer + output enable fields (Active Low). + description: Specifier for enabling the ACSPCIE PAD outputs to drive + the reference clock to the Endpoint device. + ti,syscon-pcie-ctrl: $ref: /schemas/types.yaml#/definitions/phandle-array items: |