diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-24 23:17:14 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-24 23:17:14 +0300 |
| commit | 17cd4d6f05087ea1ae5c1416ef260e5b7fc5d5c9 (patch) | |
| tree | bf06872140bc74115625e34f590b9ccc6270cbd6 /Documentation | |
| parent | 72bffe7e1eb6cb82b90aa14cd786f3f5ede9e0ae (diff) | |
| parent | 72206cc730b5c9208e9a99ace1c619f542035312 (diff) | |
| download | linux-17cd4d6f05087ea1ae5c1416ef260e5b7fc5d5c9.tar.xz | |
Merge tag 'tty-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty / serial driver updates from Greg KH:
"Here is the big set of serial and tty driver updates for 6.3-rc1.
Once again, Jiri and Ilpo have done a number of core vt and tty/serial
layer cleanups that were much needed and appreciated. Other than that,
it's just a bunch of little tty/serial driver updates:
- qcom-geni-serial driver updates
- liteuart driver updates
- hvcs driver cleanups
- n_gsm updates and additions for new features
- more 8250 device support added
- fpga/dfl update and additions
- imx serial driver updates
- fsl_lpuart updates
- other tiny fixes and updates for serial drivers
All of these have been in linux-next for a while with no reported
problems"
* tag 'tty-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (143 commits)
tty: n_gsm: add keep alive support
serial: imx: remove a redundant check
dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties
soc: qcom: geni-se: Move qcom-geni-se.h to linux/soc/qcom/geni-se.h
tty: n_gsm: add TIOCMIWAIT support
tty: n_gsm: add RING/CD control support
tty: n_gsm: mark unusable ioctl structure fields accordingly
serial: imx: get rid of registers shadowing
serial: imx: refine local variables in rxint()
serial: imx: stop using USR2 in FIFO reading loop
serial: imx: remove redundant USR2 read from FIFO reading loop
serial: imx: do not break from FIFO reading loop prematurely
serial: imx: do not sysrq broken chars
serial: imx: work-around for hardware RX flood
serial: imx: factor-out common code to imx_uart_soft_reset()
serial: 8250_pci1xxxx: Add power management functions to quad-uart driver
serial: 8250_pci1xxxx: Add RS485 support to quad-uart driver
serial: 8250_pci1xxxx: Add driver for quad-uart support
serial: 8250_pci: Add serial8250_pci_setup_port definition in 8250_pcilib.c
tty: pcn_uart: fix memory leak with using debugfs_lookup()
...
Diffstat (limited to 'Documentation')
26 files changed, 340 insertions, 157 deletions
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 276a793168a6..8faec13961cd 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1172,10 +1172,10 @@ specified, the serial port must already be setup and configured. - uart[8250],io,<addr>[,options] - uart[8250],mmio,<addr>[,options] - uart[8250],mmio32,<addr>[,options] - uart[8250],mmio32be,<addr>[,options] + uart[8250],io,<addr>[,options[,uartclk]] + uart[8250],mmio,<addr>[,options[,uartclk]] + uart[8250],mmio32,<addr>[,options[,uartclk]] + uart[8250],mmio32be,<addr>[,options[,uartclk]] uart[8250],0x<addr>[,options] Start an early, polled-mode console on the 8250/16550 UART at the specified I/O port or MMIO address. @@ -1184,7 +1184,9 @@ If none of [io|mmio|mmio32|mmio32be], <addr> is assumed to be equivalent to 'mmio'. 'options' are specified in the same format described for "console=ttyS<n>"; if - unspecified, the h/w is not initialized. + unspecified, the h/w is not initialized. 'uartclk' is + the uart clock frequency; if unspecified, it is set + to 'BASE_BAUD' * 16. pl011,<addr> pl011,mmio32,<addr> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 34b8e59aa9d4..c55865fd371a 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -62,7 +62,6 @@ properties: - const: mrvl,pxa-uart - const: nuvoton,wpcm450-uart - const: nuvoton,npcm750-uart - - const: nuvoton,npcm845-uart - const: nvidia,tegra20-uart - const: nxp,lpc3220-uart - items: @@ -94,6 +93,10 @@ properties: - ns16550a - items: - enum: + - nuvoton,npcm845-uart + - const: nuvoton,npcm750-uart + - items: + - enum: - ralink,mt7620a-uart - ralink,rt3052-uart - ralink,rt3883-uart @@ -200,12 +203,13 @@ properties: deprecated: true aspeed,lpc-io-reg: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 description: | The VUART LPC address. Only applicable to aspeed,ast2500-vuart. aspeed,lpc-interrupts: - $ref: "/schemas/types.yaml#/definitions/uint32-array" + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 maxItems: 2 description: | diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml index 53dc1212ad2e..eb3488d8f9ee 100644 --- a/Documentation/devicetree/bindings/serial/8250_omap.yaml +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -70,11 +70,6 @@ properties: dsr-gpios: true rng-gpios: true dcd-gpios: true - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - rs485-rts-active-high: true - linux,rs485-enabled-at-boot-time: true rts-gpio: true power-domains: true clock-frequency: true @@ -109,12 +104,12 @@ else: examples: - | - serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; + serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 7822705ad16c..3cbdde85ed71 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -19,6 +19,9 @@ description: | is active since power-on and does not need any clock gating and is usable as very early serial console. +allOf: + - $ref: serial.yaml# + properties: compatible: oneOf: @@ -69,14 +72,14 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x84c0 0x14>; - interrupts = <26>; - clocks = <&xtal>, <&pclk>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; + compatible = "amlogic,meson-gx-uart"; + reg = <0x84c0 0x14>; + interrupts = <26>; + clocks = <&xtal>, <&pclk>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index 876b8cf1cafb..a8b323d7bf94 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -9,9 +9,6 @@ title: Cadence UART Controller maintainers: - Michal Simek <michal.simek@xilinx.com> -allOf: - - $ref: /schemas/serial.yaml# - properties: compatible: oneOf: @@ -46,6 +43,9 @@ properties: port does not use this pin. type: boolean + power-domains: + maxItems: 1 + required: - compatible - reg @@ -53,14 +53,25 @@ required: - clocks - clock-names +allOf: + - $ref: serial.yaml# + - if: + properties: + compatible: + contains: + const: cdns,uart-r1p8 + then: + properties: + power-domains: false + unevaluatedProperties: false examples: - | uart0: serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "uart_clk", "pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0 27 4>; }; diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml index 8b643bae3c7b..920539926d7e 100644 --- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml @@ -16,7 +16,7 @@ maintainers: - Chester Lin <clin@suse.com> allOf: - - $ref: "serial.yaml" + - $ref: serial.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml index 9d949296a142..4cbe76e1715b 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -10,8 +10,8 @@ maintainers: - Fabio Estevam <festevam@gmail.com> allOf: - - $ref: "serial.yaml" - - $ref: "rs485.yaml" + - $ref: serial.yaml# + - $ref: rs485.yaml# properties: compatible: @@ -83,13 +83,6 @@ properties: are sensible for most use cases. If you need low latency processing on slow connections this needs to be configured appropriately. - uart-has-rtscts: true - - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index 74f75f669e77..ab81722293d3 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -10,7 +10,8 @@ maintainers: - Fugang Duan <fugang.duan@nxp.com> allOf: - - $ref: "rs485.yaml" + - $ref: rs485.yaml# + - $ref: serial.yaml# properties: compatible: @@ -64,9 +65,6 @@ properties: - const: rx - const: tx - rs485-rts-active-low: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml index 14c7594c88c6..6a400a5e6fc7 100644 --- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml @@ -10,7 +10,7 @@ maintainers: - Fabio Estevam <festevam@gmail.com> allOf: - - $ref: "serial.yaml" + - $ref: serial.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index 80af72859876..9571041030b7 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -10,6 +10,7 @@ maintainers: - Rob Herring <robh@kernel.org> allOf: + - $ref: /schemas/arm/primecell.yaml# - $ref: serial.yaml# # Need a custom select here or 'arm,primecell' will match on lots of nodes diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt deleted file mode 100644 index ce8c90161959..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* MSM Serial UART - -The MSM serial UART hardware is designed for low-speed use cases where a -dma-engine isn't needed. From a software perspective it's mostly compatible -with the MSM serial UARTDM except that it only supports reading and writing one -character at a time. - -Required properties: -- compatible: Should contain "qcom,msm-uart" -- reg: Should contain UART register location and length. -- interrupts: Should contain UART interrupt. -- clocks: Should contain the core clock. -- clock-names: Should be "core". - -Example: - -A uart device at 0xa9c00000 with interrupt 11. - -serial@a9c00000 { - compatible = "qcom,msm-uart"; - reg = <0xa9c00000 0x1000>; - interrupts = <11>; - clocks = <&uart_cxc>; - clock-names = "core"; -}; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml new file mode 100644 index 000000000000..a052aaef21f4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM SoC Serial UART + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: + The MSM serial UART hardware is designed for low-speed use cases where a + dma-engine isn't needed. From a software perspective it's mostly compatible + with the MSM serial UARTDM except that it only supports reading and writing + one character at a time. + +properties: + compatible: + const: qcom,msm-uart + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +unevaluatedProperties: false + +allOf: + - $ref: /schemas/serial/serial.yaml# + +examples: + - | + serial@a9c00000 { + compatible = "qcom,msm-uart"; + reg = <0xa9c00000 0x1000>; + interrupts = <11>; + clocks = <&uart_cxc>; + clock-names = "core"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml index b25aca733b72..12d0fa34f9f9 100644 --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -66,9 +66,9 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> uart0: serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; + compatible = "renesas,em-uart"; + reg = <0xe1020000 0x38>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml index 1957b9d782e8..afedb6edfc34 100644 --- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -131,20 +131,20 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7795-sysc.h> aliases { - serial1 = &hscif1; + serial1 = &hscif1; }; hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0xe6550000 96>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - uart-has-rtscts; + compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0xe6550000 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + uart-has-rtscts; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml index bf7708a7a2c0..dc445b327e0b 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml @@ -91,19 +91,19 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> aliases { - serial0 = &sci0; + serial0 = &sci0; }; sci0: serial@1004d000 { - compatible = "renesas,r9a07g044-sci", "renesas,sci"; - reg = <0x1004d000 0x400>; - interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCI0_RST>; + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0x1004d000 0x400>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index f81f2d67a1ed..1989bd67d04e 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -180,19 +180,19 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7791-sysc.h> aliases { - serial0 = &scif0; + serial0 = &scif0; }; scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0xe6e60000 64>; - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; + compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0xe6e60000 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml index 3c67d3202e1b..4c3b5e7270da 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml @@ -95,18 +95,18 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a7790-sysc.h> aliases { - serial0 = &scifa0; + serial0 = &scifa0; }; scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", - "renesas,scifa"; - reg = <0xe6c40000 64>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; + compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", + "renesas,scifa"; + reg = <0xe6c40000 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml index d5571c7a4424..2f7cbbb48960 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml @@ -94,10 +94,10 @@ examples: #include <dt-bindings/clock/r8a7740-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> scifb: serial@e6c30000 { - compatible = "renesas,scifb-r8a7740", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; }; diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 789763cf427a..303a443d9e29 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -51,6 +51,12 @@ properties: description: GPIO pin to enable RS485 bus termination. maxItems: 1 + rs485-rx-during-tx-gpios: + description: Output GPIO pin that sets the state of rs485-rx-during-tx. This + signal can be used to control the RX part of an RS485 transceiver. Thereby + the active state enables RX during TX. + maxItems: 1 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml index 11e822bf09e2..e05ad3ac2abc 100644 --- a/Documentation/devicetree/bindings/serial/serial.yaml +++ b/Documentation/devicetree/bindings/serial/serial.yaml @@ -141,13 +141,13 @@ additionalProperties: true examples: - | serial@1234 { - compatible = "ns16550a"; - reg = <0x1234 0x20>; - interrupts = <1>; - - bluetooth { - compatible = "brcm,bcm4330-bt"; - interrupt-parent = <&gpio>; - interrupts = <10>; - }; + compatible = "ns16550a"; + reg = <0x1234 0x20>; + interrupts = <1>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + interrupt-parent = <&gpio>; + interrupts = <10>; + }; }; diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index b0a8871e3641..b0df1cac4968 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -53,13 +53,13 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/clock/sifive-fu540-prci.h> - serial@10010000 { + #include <dt-bindings/clock/sifive-fu540-prci.h> + serial@10010000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; interrupt-parent = <&plic0>; interrupts = <80>; reg = <0x10010000 0x1000>; clocks = <&prci FU540_PRCI_CLK_TLCLK>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index b9c2287c5d1e..2becdfab4f15 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -67,6 +67,14 @@ properties: - const: baudclk - const: apb_pclk + dmas: + minItems: 2 + + dma-names: + items: + - const: rx + - const: tx + snps,uart-16550-compatible: description: reflects the value of UART_16550_COMPATIBLE configuration parameter. Define this if your UART does not implement the busy functionality. diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 85876c668f6d..1df8ffe95fc6 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -35,8 +35,6 @@ properties: description: enable hardware flow control (deprecated) $ref: /schemas/types.yaml#/definitions/flag - uart-has-rtscts: true - rx-tx-swap: true dmas: @@ -60,11 +58,6 @@ properties: wakeup-source: true - rs485-rts-delay: true - rs485-rts-active-low: true - linux,rs485-enabled-at-boot-time: true - rs485-rx-during-tx: true - rx-threshold: description: If value is set to 1, RX FIFO threshold is disabled. diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml index 2f4390e8d4e8..08dcb275d8e2 100644 --- a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml @@ -63,7 +63,7 @@ required: - xlnx,use-parity allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# - if: properties: xlnx,use-parity: @@ -76,7 +76,7 @@ unevaluatedProperties: false examples: - | - serial@800c0000 { + serial@800c0000 { compatible = "xlnx,xps-uartlite-1.00.a"; reg = <0x800c0000 0x10000>; interrupts = <0x0 0x6e 0x1>; @@ -84,5 +84,5 @@ examples: current-speed = <115200>; xlnx,data-bits = <8>; xlnx,use-parity = <0>; - }; + }; ... diff --git a/Documentation/driver-api/tty/n_gsm.rst b/Documentation/driver-api/tty/n_gsm.rst index 35d7381515b0..9447b8a3b8e2 100644 --- a/Documentation/driver-api/tty/n_gsm.rst +++ b/Documentation/driver-api/tty/n_gsm.rst @@ -25,6 +25,8 @@ Config Initiator #. Switch the serial line to using the n_gsm line discipline by using ``TIOCSETD`` ioctl. +#. Configure the mux using ``GSMIOC_GETCONF_EXT``/``GSMIOC_SETCONF_EXT`` ioctl if needed. + #. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl. #. Obtain base gsmtty number for the used serial port. @@ -42,6 +44,7 @@ Config Initiator int ldisc = N_GSM0710; struct gsm_config c; + struct gsm_config_ext ce; struct termios configuration; uint32_t first; @@ -62,6 +65,12 @@ Config Initiator /* use n_gsm line discipline */ ioctl(fd, TIOCSETD, &ldisc); + /* get n_gsm extended configuration */ + ioctl(fd, GSMIOC_GETCONF_EXT, &ce); + /* use keep-alive once every 5s for modem connection supervision */ + ce.keep_alive = 500; + /* set the new extended configuration */ + ioctl(fd, GSMIOC_SETCONF_EXT, &ce); /* get n_gsm configuration */ ioctl(fd, GSMIOC_GETCONF, &c); /* we are initiator and need encoding 0 (basic) */ @@ -106,6 +115,9 @@ Config Requester #. Switch the serial line to using the *n_gsm* line discipline by using ``TIOCSETD`` ioctl. +#. Configure the mux using ``GSMIOC_GETCONF_EXT``/``GSMIOC_SETCONF_EXT`` + ioctl if needed. + #. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl. #. Obtain base gsmtty number for the used serial port:: @@ -119,6 +131,7 @@ Config Requester int ldisc = N_GSM0710; struct gsm_config c; + struct gsm_config_ext ce; struct termios configuration; uint32_t first; @@ -132,6 +145,12 @@ Config Requester /* use n_gsm line discipline */ ioctl(fd, TIOCSETD, &ldisc); + /* get n_gsm extended configuration */ + ioctl(fd, GSMIOC_GETCONF_EXT, &ce); + /* use keep-alive once every 5s for peer connection supervision */ + ce.keep_alive = 500; + /* set the new extended configuration */ + ioctl(fd, GSMIOC_SETCONF_EXT, &ce); /* get n_gsm configuration */ ioctl(fd, GSMIOC_GETCONF, &c); /* we are requester and need encoding 0 (basic) */ diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 15b670926084..80255e2dc3e6 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -75,6 +75,125 @@ convenient for software to locate each feature by walking through this list, and can be implemented in register regions of any FPGA device. +Device Feature Header - Version 0 +================================= +Version 0 (DFHv0) is the original version of the Device Feature Header. +All multi-byte quantities in DFHv0 are little-endian. +The format of DFHv0 is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + +- Offset 0x00 + + * Type - The type of DFH (e.g. FME, AFU, or private feature). + * DFH VER - The version of the DFH. + * Rsvd - Currently unused. + * EOL - Set if the DFH is the end of the Device Feature List (DFL). + * Next - The offset in bytes of the next DFH in the DFL from the DFH start, + and the start of a DFH must be aligned to an 8 byte boundary. + If EOL is set, Next is the size of MMIO of the last feature in the list. + * REV - The revision of the feature associated with this header. + * ID - The feature ID if Type is private feature. + +- Offset 0x08 + + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier + (present only if Type is FME or AFU). + +- Offset 0x10 + + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier + (present only if Type is FME or AFU). + + +Device Feature Header - Version 1 +================================= +Version 1 (DFHv1) of the Device Feature Header adds the following functionality: + +* Provides a standardized mechanism for features to describe + parameters/capabilities to software. +* Standardize the use of a GUID for all DFHv1 types. +* Decouples the DFH location from the register space of the feature itself. + +All multi-byte quantities in DFHv1 are little-endian. +The format of Version 1 of the Device Feature Header (DFH) is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + |63 Reg Address/Offset 1| Rel 0| 0x18 + +-----------------------------------------------------------------------+ + |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20 + +-----------------------------------------------------------------------+ + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28 + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| 0x30 + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + +- Offset 0x00 + + * Type - The type of DFH (e.g. FME, AFU, or private feature). + * DFH VER - The version of the DFH. + * Rsvd - Currently unused. + * EOL - Set if the DFH is the end of the Device Feature List (DFL). + * Next - The offset in bytes of the next DFH in the DFL from the DFH start, + and the start of a DFH must be aligned to an 8 byte boundary. + If EOL is set, Next is the size of MMIO of the last feature in the list. + * REV - The revision of the feature associated with this header. + * ID - The feature ID if Type is private feature. + +- Offset 0x08 + + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier. + +- Offset 0x10 + + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier. + +- Offset 0x18 + + * Reg Address/Offset - If Rel bit is set, then the value is the high 63 bits + of a 16-bit aligned absolute address of the feature's registers. Otherwise + the value is the offset from the start of the DFH of the feature's registers. + +- Offset 0x20 + + * Reg Size - Size of feature's register set in bytes. + * Params - Set if DFH has a list of parameter blocks. + * Group - Id of group if feature is part of a group. + * Instance - Id of feature instance within a group. + +- Offset 0x28 if feature has parameters + + * Next - Offset to the next parameter block in 8 byte words. If EOP set, + size in 8 byte words of last parameter. + * Param Version - Version of Param ID. + * Param ID - ID of parameter. + +- Offset 0x30 + + * Parameter Data - Parameter data whose size and format is defined by + version and ID of the parameter. + + FIU - FME (FPGA Management Engine) ================================== The FPGA Management Engine performs reconfiguration and other infrastructure |