dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock generator

Add bindings for the Image-Signal-Process clock generator (ISP)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

1 files changed, 97 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml
new file mode 100644
index 000000000000..3b1c8bff7471
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clk-isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 ISP Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clk-isp
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: DVP clock
+      - description: ISP CORE_2X clock
+      - description: ISP AXI clock
+      - description: NOC_BUS ISP clock
+
+  clock-names:
+    items:
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_dvp
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi
+      - const: u0_sft7110_noc_bus_clk_isp_axi
+
+  resets:
+    items:
+      - description: ISP reset
+      - description: ISP AXI reset
+      - description: NOC_BUS ISP reset
+
+  reset-names:
+    items:
+      - const: rst_isp_top_n
+      - const: rst_isp_top_axi
+      - const: rst_isp_noc_bus_n
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-clk-isp.h> for valid indices.
+
+  power-domains:
+    maxItems: 1
+    description:
+      ISP domain power
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - '#clock-cells'
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    #include <dt-bindings/clock/starfive-jh7110-clk-isp.h>
+    clkisp: clock-controller@19810000 {
+        compatible = "starfive,jh7110-clk-isp";
+        reg = <0x0 0x19810000 0x0 0x10000>;
+        reg-names = "isp";
+        #clock-cells = <1>;
+        clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
+                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
+        clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
+                      "u0_sft7110_noc_bus_clk_isp_axi";
+        resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
+                 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
+        reset-names = "rst_isp_top_n", "rst_isp_top_axi",
+                      "rst_isp_noc_bus_n";
+        power-domains = <&pwrc JH7110_PD_ISP>;
+    };