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| author | Chew, Chiau Ee <chiau.ee.chew@intel.com> | 2014-03-11 15:33:45 +0400 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2014-03-12 11:14:04 +0400 |
| commit | 8efd1e9ee3bd55e20cb36e56ca53096cf2b3a930 (patch) | |
| tree | db5abf2de8a390ddf456e2ac7f899f65c93bf7e8 /Documentation/i2c/functionality | |
| parent | 4fda99627dc037d3b316c3b3250075645cfcbe4d (diff) | |
| download | linux-8efd1e9ee3bd55e20cb36e56ca53096cf2b3a930.tar.xz | |
i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'Documentation/i2c/functionality')
0 files changed, 0 insertions, 0 deletions