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authorWolfram Sang <wsa@the-dreams.de>2020-01-29 23:56:36 +0300
committerWolfram Sang <wsa@the-dreams.de>2020-01-29 23:56:36 +0300
commit6810df46c41879eba8437ab020c7abf5d1db827e (patch)
treea9af691033e81bd6396a63b29a323296df69c2bf /Documentation/devicetree
parent878508aed4776a5b08dcc000d33a01a42e3fd07d (diff)
parentcd5676db0574cc1c0b234bc3b17565b07290aa72 (diff)
downloadlinux-6810df46c41879eba8437ab020c7abf5d1db827e.tar.xz
Merge tag 'at24-updates-for-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-5.6
at24 updates for linux v5.6 - minor maintenance: update the license tag, sort headers - move support for the write-protect pin into nvmem core - add a reference to the new wp-gpios property in nvmem to at25 bindings - add support for regulator and pm_runtime control
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/eeprom/at24.yaml9
-rw-r--r--Documentation/devicetree/bindings/eeprom/at25.txt2
-rw-r--r--Documentation/devicetree/bindings/nvmem/nvmem.yaml11
3 files changed, 18 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml
index e8778560d966..0f6d8db18d6c 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at24.yaml
@@ -145,10 +145,7 @@ properties:
over reads to the next slave address. Please consult the manual of
your device.
- wp-gpios:
- description:
- GPIO to which the write-protect pin of the chip is connected.
- maxItems: 1
+ wp-gpios: true
address-width:
allOf:
@@ -167,6 +164,10 @@ properties:
minimum: 1
maximum: 8
+ vcc-supply:
+ description:
+ phandle of the regulator that provides the supply voltage.
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/eeprom/at25.txt b/Documentation/devicetree/bindings/eeprom/at25.txt
index 42577dd113dd..fcacd97abd0a 100644
--- a/Documentation/devicetree/bindings/eeprom/at25.txt
+++ b/Documentation/devicetree/bindings/eeprom/at25.txt
@@ -20,6 +20,7 @@ Optional properties:
- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
- read-only : this parameter-less property disables writes to the eeprom
+- wp-gpios : GPIO to which the write-protect pin of the chip is connected
Obsolete legacy properties can be used in place of "size", "pagesize",
"address-width", and "read-only":
@@ -36,6 +37,7 @@ Example:
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
+ wp-gpios = <&gpio1 3 0>;
pagesize = <64>;
size = <32768>;
diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
index 1c75a059206c..b43c6c65294e 100644
--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
@@ -34,6 +34,14 @@ properties:
description:
Mark the provider as read only.
+ wp-gpios:
+ description:
+ GPIO to which the write-protect pin of the chip is connected.
+ The write-protect GPIO is asserted, when it's driven high
+ (logical '1') to block the write operation. It's deasserted,
+ when it's driven low (logical '0') to allow writing.
+ maxItems: 1
+
patternProperties:
"^.*@[0-9a-f]+$":
type: object
@@ -63,9 +71,12 @@ patternProperties:
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
+
qfprom: eeprom@700000 {
#address-cells = <1>;
#size-cells = <1>;
+ wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
/* ... */