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authorPalmer Dabbelt <palmer@rivosinc.com>2023-01-06 21:31:12 +0300
committerPalmer Dabbelt <palmer@rivosinc.com>2023-01-06 21:31:12 +0300
commit6710e07f01b54b2d93e81cfe1c207d39d4fdb9a8 (patch)
treef56e019560d3841de7b48f69b5db12da92686eef /Documentation/devicetree
parentb9b916aee6715cd7f3318af6dc360c4729417b94 (diff)
parenta943385aa80151c6b2611d3a1cf8338af2b257a1 (diff)
downloadlinux-6710e07f01b54b2d93e81cfe1c207d39d4fdb9a8.tar.xz
Merge patch series "riscv,isa fixups"
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid. * b4-shazam-merge: dt-bindings: riscv: fix single letter canonical order dt-bindings: riscv: fix underscore requirement for multi-letter extensions Link: https://lore.kernel.org/r/20221205174459.60195-1-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/riscv/cpus.yaml2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6720764e765..a2884e3113da 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -83,7 +83,7 @@ properties:
insensitive, letters in the riscv,isa string must be all
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
- pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false