Merge branch 'pm-devfreq'

* pm-devfreq: (24 commits)
  PM / devfreq: Add debugfs support with devfreq_summary file
  PM / devfreq: exynos: Rename Exynos to lowercase
  PM / devfreq: imx8m-ddrc: Fix inconsistent IS_ERR and PTR_ERR
  PM / devfreq: exynos-bus: Add error log when fail to get devfreq-event
  PM / devfreq: exynos-bus: Disable devfreq-event device when fails
  PM / devfreq: rk3399_dmc: Disable devfreq-event device when fails
  PM / devfreq: imx8m-ddrc: Remove unused defines
  PM / devfreq: exynos-bus: Reduce goto statements and remove unused headers
  PM / devfreq: rk3399_dmc: Add COMPILE_TEST and HAVE_ARM_SMCCC dependency
  PM / devfreq: rockchip-dfi: Convert to devm_platform_ioremap_resource
  PM / devfreq: rk3399_dmc: Add missing of_node_put()
  PM / devfreq: rockchip-dfi: Add missing of_node_put()
  PM / devfreq: Fix multiple kernel-doc warnings
  PM / devfreq: exynos-bus: Extract exynos_bus_profile_init_passive()
  PM / devfreq: exynos-bus: Extract exynos_bus_profile_init()
  PM / devfreq: Move declaration of DEVICE_ATTR_RW(min_freq)
  PM / devfreq: Move statistics to separate struct devfreq_stats
  PM / devfreq: Add clearing transitions stats
  PM / devfreq: Change time stats to 64-bit
  PM / devfreq: Add new name attribute for sysfs
  ...

1 files changed, 72 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
new file mode 100644
index 000000000000..c9e6c22cb5be
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX8M DDR Controller
+
+maintainers:
+  - Leonard Crestez <leonard.crestez@nxp.com>
+
+description:
+  The DDRC block is integrated in i.MX8M for interfacing with DDR based
+  memories.
+
+  It supports switching between different frequencies at runtime but during
+  this process RAM itself becomes briefly inaccessible so actual frequency
+  switching is implemented by TF-A code which runs from a SRAM area.
+
+  The Linux driver for the DDRC doesn't even map registers (they're included
+  for the sake of "describing hardware"), it mostly just exposes firmware
+  capabilities through standard Linux mechanism like devfreq and OPP tables.
+
+properties:
+  compatible:
+    items:
+      - enum:
+        - fsl,imx8mn-ddrc
+        - fsl,imx8mm-ddrc
+        - fsl,imx8mq-ddrc
+      - const: fsl,imx8m-ddrc
+
+  reg:
+    maxItems: 1
+    description:
+      Base address and size of DDRC CTL area.
+      This is not currently mapped by the imx8m-ddrc driver.
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: core
+      - const: pll
+      - const: alt
+      - const: apb
+
+  operating-points-v2: true
+  opp-table: true
+
+required:
+  - reg
+  - compatible
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    ddrc: memory-controller@3d400000 {
+        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+        reg = <0x3d400000 0x400000>;
+        clock-names = "core", "pll", "alt", "apb";
+        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+                 <&clk IMX8MM_DRAM_PLL>,
+                 <&clk IMX8MM_CLK_DRAM_ALT>,
+                 <&clk IMX8MM_CLK_DRAM_APB>;
+        operating-points-v2 = <&ddrc_opp_table>;
+    };