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authorDavid Lechner <david@lechnology.com>2018-05-18 19:48:26 +0300
committerSekhar Nori <nsekhar@ti.com>2018-06-26 13:47:08 +0300
commit862ceabb4690c83d02d823bc712c47451714f34a (patch)
tree6db0f2be2eda5562cb3b72583df5ed5b65692301 /Documentation/devicetree/bindings/timer
parent8ae024497b3d68165e692d6ad5ba149cd070dac2 (diff)
downloadlinux-862ceabb4690c83d02d823bc712c47451714f34a.tar.xz
dt-bindings: timer: new bindings for TI DaVinci timer
This adds new device tree bindings for the timer IP block of TI DaVinci-like SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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+* Device tree bindings for Texas Instruments DaVinci timer
+
+This document provides bindings for the 64-bit timer in the DaVinci
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+The timer is a free running up-counter and can generate interrupts when the
+counter reaches preset counter values.
+
+Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
+watchdog timers.
+
+Required properties:
+
+- compatible : should be "ti,da830-timer".
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupts generated by the timer.
+- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
+ "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
+ "cmpint7" ("cmpintX" may be omitted if not present in the
+ hardware).
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+ clocksource: timer@20000 {
+ compatible = "ti,da830-timer";
+ reg = <0x20000 0x1000>;
+ interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
+ <80>, <81>;
+ interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
+ "cmpint2", "cmpint3", "cmpint4", "cmpint5",
+ "cmpint6", "cmpint7";
+ clocks = <&pll0_auxclk>;
+ };