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author | David Heidelberg <david@ixit.cz> | 2022-03-04 02:33:06 +0300 |
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committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2022-03-07 20:27:22 +0300 |
commit | cea9ffe0094d468b17814056fcebe7b3840af5f0 (patch) | |
tree | ba82460da3ce7303fa98a5940779af9e99a98a01 /Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt | |
parent | bf127df3cceada8693888fc86a3121c38ef25701 (diff) | |
download | linux-cea9ffe0094d468b17814056fcebe7b3840af5f0.tar.xz |
dt-bindings: timer: Tegra: Convert text bindings to yaml
Convert Tegra timer binding into yaml format.
This commit also merge 3 text bindings with almost
identical content (differens in number of registers).
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://lore.kernel.org/r/20220303233307.61753-1-david@ixit.cz
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt')
-rw-r--r-- | Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt deleted file mode 100644 index 4a864bd10d3d..000000000000 --- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 timer - -The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free -running counter. The first two channels may also trigger a watchdog reset. - -Required properties: - -- compatible : should be "nvidia,tegra20-timer". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-timer"; - reg = <0x60005000 0x60>; - interrupts = <0 0 0x04 - 0 1 0x04 - 0 41 0x04 - 0 42 0x04>; - clocks = <&tegra_car 132>; -}; |