diff options
| author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2022-12-13 11:24:49 +0300 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2022-12-27 01:09:29 +0300 |
| commit | 9e699b8985e62c93cb1ca84b27197b5c1cdbd596 (patch) | |
| tree | 06165c0a40c5d64dc95799bce064d7981ed8a72c /Documentation/devicetree/bindings/soc/socionext | |
| parent | 5993f6bd555e2696bb4d79cf54b976cb58793534 (diff) | |
| download | linux-9e699b8985e62c93cb1ca84b27197b5c1cdbd596.tar.xz | |
dt-bindings: soc: socionext: Add UniPhier AHCI glue layer
Add DT binding schema for components belonging to the platform-specific
AHCI glue layer implemented in UniPhier SoCs.
This AHCI glue layer works as a sideband logic for the host controller,
including core reset, PHYs, and some signals to the controller.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-18-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/soc/socionext')
| -rw-r--r-- | Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml new file mode 100644 index 000000000000..09f861cc068f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SoC AHCI glue layer + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband + logic handling signals to AHCI host controller inside AHCI component. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-pro4-ahci-glue + - socionext,uniphier-pxs2-ahci-glue + - socionext,uniphier-pxs3-ahci-glue + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^reset-controller@[0-9a-f]+$": + $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml# + + "phy@[0-9a-f]+$": + $ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sata-controller@65700000 { + compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd"; + reg = <0x65b00000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + reset-controller@0 { + compatible = "socionext,uniphier-pxs3-ahci-reset"; + reg = <0x0 0x4>; + clock-names = "link"; + clocks = <&sys_clk 28>; + reset-names = "link"; + resets = <&sys_rst 28>; + #reset-cells = <1>; + }; + + phy@10 { + compatible = "socionext,uniphier-pxs3-ahci-phy"; + reg = <0x10 0x10>; + clock-names = "link", "phy"; + clocks = <&sys_clk 28>, <&sys_clk 30>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + #phy-cells = <0>; + }; + }; |