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author | Paul Walmsley <paul.walmsley@sifive.com> | 2019-06-26 18:19:29 +0300 |
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committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-06-26 20:28:53 +0300 |
commit | 3cdb0157884344c7b40998f31ce43c4ded593cdd (patch) | |
tree | 40a5fdcdfaf17d9676208db80a803a1277eb3fd5 /Documentation/devicetree/bindings/riscv | |
parent | 45b03df2864aa4c67f6a648f0a7951116e1ef069 (diff) | |
download | linux-3cdb0157884344c7b40998f31ce43c4ded593cdd.tar.xz |
dt-bindings: riscv: resolve 'make dt_binding_check' warnings
Rob pointed out that one of the examples in the RISC-V 'cpus' YAML
schema results in warnings from 'make dt_binding_check'. Fix these.
While here, make the whitespace in the second example consistent
with the first example.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org> # for fixing the dtc warnings
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 27f02ec4bb45..f97a4ecd7b91 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -152,17 +152,19 @@ examples: - | // Example 2: Spike ISA Simulator with 1 Hart cpus { - cpu@0 { - device_type = "cpu"; - reg = <0>; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv48"; - interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; ... |