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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2018-12-20 17:44:31 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-12-21 13:50:48 +0300 |
| commit | da801ab56ad874897b0b255216767c983e665a4c (patch) | |
| tree | dba16bd10e264e2f4f989038e7a52e34726817af /Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | |
| parent | a49d784d5a8272d0f63c448fe8dc69e589db006e (diff) | |
| download | linux-da801ab56ad874897b0b255216767c983e665a4c.tar.xz | |
pinctrl: ocelot: add MSCC Jaguar2 support
Jaguar2 has the same register layout as Ocelot but it has 64 pins, meaning
that there are 2 registers instead of one.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 24a210e0c59a..32a8a8fa7805 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,7 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl" or + "mscc,jaguar2-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. |