summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/phy
diff options
context:
space:
mode:
authorRamuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>2019-12-17 04:56:57 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2020-01-14 08:20:19 +0300
commit5bc999108025a82a2862b2e7e0af00e34643d270 (patch)
tree89f76e1f896906994fc5b03a80ef5416a51a0e15 /Documentation/devicetree/bindings/phy
parent091876cc355d6739e393efa4b3d07f451a6a035c (diff)
downloadlinux-5bc999108025a82a2862b2e7e0af00e34643d270.tar.xz
dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY
Add a YAML schema to use the host controller driver with the eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml56
1 files changed, 56 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml
new file mode 100644
index 000000000000..ff7959c21af0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings
+
+maintainers:
+ - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
+
+description: |+
+ Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
+ node is used to reference the base address of eMMC phy registers.
+
+ The eMMC PHY node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+ "intel,lgm-syscon", "syscon"
+ - reg:
+ maxItems: 1
+
+properties:
+ compatible:
+ const: intel,lgm-emmc-phy
+
+ "#phy-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ sysconf: chiptop@e0200000 {
+ compatible = "intel,lgm-syscon", "syscon";
+ reg = <0xe0200000 0x100>;
+
+ emmc-phy: emmc-phy@a8 {
+ compatible = "intel,lgm-emmc-phy";
+ reg = <0x00a8 0x10>;
+ clocks = <&emmc>;
+ #phy-cells = <0>;
+ };
+ };
+...