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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2012-09-05 09:57:19 +0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2012-09-05 09:57:19 +0400
commite6c340171f0daaccc95b90abbeed2b837157ee11 (patch)
tree843d4035be59bd791321910e52157ce527b3b4b3 /Documentation/devicetree/bindings/mips/cavium/ciu.txt
parenta85442ade272121927a56e02f7dfde1127482df2 (diff)
parent4cbe5a555fa58a79b6ecbb6c531b8bab0650778d (diff)
downloadlinux-e6c340171f0daaccc95b90abbeed2b837157ee11.tar.xz
Merge tag 'v3.6-rc4' into next
Linux 3.6-rc4 # gpg: Signature made Sat 01 Sep 2012 10:40:33 AM PDT using RSA key ID 00411886 # gpg: Good signature from "Linus Torvalds <torvalds@linux-foundation.org>"
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+* Central Interrupt Unit
+
+Properties:
+- compatible: "cavium,octeon-3860-ciu"
+
+ Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
+
+- interrupt-controller: This is an interrupt controller.
+
+- reg: The base address of the CIU's register bank.
+
+- #interrupt-cells: Must be <2>. The first cell is the bank within
+ the CIU and may have a value of 0 or 1. The second cell is the bit
+ within the bank and may have a value between 0 and 63.
+
+Example:
+ interrupt-controller@1070000000000 {
+ compatible = "cavium,octeon-3860-ciu";
+ interrupt-controller;
+ /* Interrupts are specified by two parts:
+ * 1) Controller register (0 or 1)
+ * 2) Bit within the register (0..63)
+ */
+ #interrupt-cells = <2>;
+ reg = <0x10700 0x00000000 0x0 0x7000>;
+ };