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authorMagnus Damm <damm+renesas@opensource.se>2014-12-03 15:18:03 +0300
committerThomas Gleixner <tglx@linutronix.de>2015-01-26 13:38:22 +0300
commite03f9088e22ca7e2b0de826466540e2527518e52 (patch)
tree78e192dab008ea8852d9fb57836338d160ed96af /Documentation/devicetree/bindings/interrupt-controller
parent64c96a57b73397415eafa4ac2020ea7d99d7168c (diff)
downloadlinux-e03f9088e22ca7e2b0de826466540e2527518e52.tar.xz
irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support
Add r8a7779 specific support for IRLM bit configuration in the INTC-IRQPIN driver. Without this code we need special workaround code in arch/arm/mach-shmobile. The IRLM bit for the INTC hardware exists on various older SH-based SoCs and is used to select between two modes for the external interrupt pins IRQ0 to IRQ3: IRLM = 0: (default from reset on r8a7779) In this mode the pins IRQ0 to IRQ3 are used together to give a value between 0 and 15 to the SoC. External logic is required for masking. This mode is not supported by the INTC-IRQPIN driver. IRLM = 1: (needs this patch or configuration elsewhere) In this mode IRQ0 to IRQ3 operate as 4 individual external interrupt pins. In this mode the SMSC ethernet chip can be used via IRQ1 on r8a7779 Marzen. This mode is the only supported mode by the INTC-IRQPIN driver. For this patch to work the r8a7779 DTS needs to pass the ICR0 register as the last register bank. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: horms@verge.net.au Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/20141203121803.5936.35881.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller')
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
index c73acd060093..4f7946ae8adc 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -9,6 +9,11 @@ Required properties:
- "renesas,intc-irqpin-r8a7778" (R-Car M1A)
- "renesas,intc-irqpin-r8a7779" (R-Car H1)
- "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
+
+- reg: Base address and length of each register bank used by the external
+ IRQ pins driven by the interrupt controller hardware module. The base
+ addresses, length and number of required register banks varies with soctype.
+
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory