Merge tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS upates from Thomas Bogendoerfer:

 - improvements for Loongson64

 - extended ingenic support

 - removal of not maintained paravirt system type

 - cleanups and fixes

* tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (81 commits)
  MIPS: SGI-IP27: always enable NUMA in Kconfig
  MAINTAINERS: Update KVM/MIPS maintainers
  MIPS: Update default config file for Loongson-3
  MIPS: KVM: Add kvm guest support for Loongson-3
  dt-bindings: mips: Document Loongson kvm guest board
  MIPS: handle Loongson-specific GSExc exception
  MIPS: add definitions for Loongson-specific CP0.Diag1 register
  MIPS: only register FTLBPar exception handler for supported models
  MIPS: ingenic: Hardcode mem size for qi,lb60 board
  MIPS: DTS: ingenic/qi,lb60: Add model and memory node
  MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB
  MIPS: head.S: Init fw_passed_dtb to builtin DTB
  of: address: Fix parser address/size cells initialization
  of_address: Guard of_bus_pci_get_flags with CONFIG_PCI
  MIPS: DTS: Fix number of msi vectors for Loongson64G
  MIPS: Loongson64: Add ISA node for LS7A PCH
  MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCH
  MIPS: Loongson64: Enlarge IO_SPACE_LIMIT
  MIPS: Loongson64: Process ISA Node in DeviceTree
  of_address: Add bus type match for pci ranges parser
  ...

1 files changed, 0 insertions, 67 deletions

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
deleted file mode 100644
index 173595305e26..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-MIPS Global Interrupt Controller (GIC)
-
-The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
-It also supports local (per-processor) interrupts and software-generated
-interrupts which can be used as IPIs.  The GIC also includes a free-running
-global timer, per-CPU count/compare timers, and a watchdog.
-
-Required properties:
-- compatible : Should be "mti,gic".
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt specifier.  Should be 3.
-  - The first cell is the type of interrupt, local or shared.
-    See <include/dt-bindings/interrupt-controller/mips-gic.h>.
-  - The second cell is the GIC interrupt number.
-  - The third cell encodes the interrupt flags.
-    See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
-    flags.
-
-Optional properties:
-- reg : Base address and length of the GIC registers.  If not present,
-  the base address reported by the hardware GCR_GIC_BASE will be used.
-- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
-  to which the GIC may not route interrupts.  Valid values are 2 - 7.
-  This property is ignored if the CPU is started in EIC mode.
-- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
-  reserved for IPIs.
-  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
-  of the reserved range.
-  If not specified, the driver will allocate the last 2 * number of VPEs in the
-  system.
-
-Required properties for timer sub-node:
-- compatible : Should be "mti,gic-timer".
-- interrupts : Interrupt for the GIC local timer.
-
-Optional properties for timer sub-node:
-- clocks : GIC timer operating clock.
-- clock-frequency : Clock frequency at which the GIC timers operate.
-
-Note that one of clocks or clock-frequency must be specified.
-
-Example:
-
-	gic: interrupt-controller@1bdc0000 {
-		compatible = "mti,gic";
-		reg = <0x1bdc0000 0x20000>;
-
-		interrupt-controller;
-		#interrupt-cells = <3>;
-
-		mti,reserved-cpu-vectors = <7>;
-		mti,reserved-ipi-vectors = <40 8>;
-
-		timer {
-			compatible = "mti,gic-timer";
-			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-			clock-frequency = <50000000>;
-		};
-	};
-
-	uart@18101400 {
-		...
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-		...
-	};