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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2016-08-05 17:55:18 +0300
committerJason Cooper <jason@lakedaemon.net>2016-08-16 16:59:04 +0300
commit33a6c324a7266462f933ab25a92383c882e4b4f1 (patch)
tree40031ccbe38e5ccae4744afab1b89d8d4f630df6 /Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt
parent29b4817d4018df78086157ea3a55c1d9424a7cfc (diff)
downloadlinux-33a6c324a7266462f933ab25a92383c882e4b4f1.tar.xz
dt-bindings: interrupt-controller: add DT binding for Marvell 7K/8K PIC
This commit adds the Device Tree binding description for the PIC interrupt controller available in the ARM64 Marvell Armada 7K/8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/1470408921-447-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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+Marvell Armada 7K/8K PIC Interrupt controller
+---------------------------------------------
+
+This is the Device Tree binding for the PIC, a secondary interrupt
+controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
+typically connected to the GIC as the primary interrupt controller.
+
+Required properties:
+- compatible: should be "marvell,armada-8k-pic"
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: the number of cells to define interrupts on this
+ controller. Should be 1
+- reg: the register area for the PIC interrupt controller
+- interrupts: the interrupt to the primary interrupt controller,
+ typically the GIC
+
+Example:
+
+ pic: interrupt-controller@3f0100 {
+ compatible = "marvell,armada-8k-pic";
+ reg = <0x3f0100 0x10>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };