diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-15 22:49:41 +0300 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-15 22:49:41 +0300 |
commit | 6df8b74b1720db1133ace0861cb6721bfe57819a (patch) | |
tree | 9bf00c9a75cd52a0917bbd6ff5ff4a693b3b8f0a /Documentation/devicetree/bindings/fpga | |
parent | 57d64e6f5fac7b47dd03487f5f2670a7f0c67335 (diff) | |
parent | 61eb3a04f9789c5e4f7498a2f171b82a567cea6b (diff) | |
download | linux-6df8b74b1720db1133ace0861cb6721bfe57819a.tar.xz |
Merge tag 'devicetree-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull DeviceTree updates from Rob Herring:
- add various vendor prefixes.
- fix NUMA node handling when "numa=off" is passed on kernel command
line.
- coding style Clean-up of overlay handling code.
- DocBook fixes in DT platform driver code
- Altera SoCFPGA binding addtions for freeze bridge, arria10 FPGA
manager and FPGA bridges.
- a couple of printk message fixes.
* tag 'devicetree-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (33 commits)
dt: pwm: bcm2835: fix typo in clocks property name
devicetree: add vendor prefix for National Instruments
Revert "of: base: add support to get machine model name"
of: Fix issue where code would fall through to error case.
drivers/of: fix missing pr_cont()s in of_print_phandle_args
devicetree: bindings: Add vendor prefix for Oki
devicetree: bindings: Add vendor prefix for Andes Technology Corporation
dt-bindings: add MYIR Tech hardware vendor prefix
add bindings document for altera freeze bridge
ARM: socfpga: add bindings doc for arria10 fpga manager
ARM: socfpga: add bindings document for fpga bridge drivers
of: base: add support to get machine model name
of/platform: clarify of_find_device_by_node refcounting
of/platform: fix of_platform_device_destroy comment
of: Remove unused variable overlay_symbols
of: Move setting of pointer to beside test for non-null
of: Add back an error message, restructured
of: Update comments to reflect changes and increase clarity
of: Remove redundant size check
of: Update structure of code to be clearer, also remove BUG_ON()
...
Diffstat (limited to 'Documentation/devicetree/bindings/fpga')
4 files changed, 97 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt new file mode 100644 index 000000000000..817a8d4bf903 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt @@ -0,0 +1,16 @@ +Altera FPGA To SDRAM Bridge Driver + +Required properties: +- compatible : Should contain "altr,socfpga-fpga2sdram-bridge" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + bridge-enable = <0>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt new file mode 100644 index 000000000000..f8e288c71b2d --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt @@ -0,0 +1,23 @@ +Altera Freeze Bridge Controller Driver + +The Altera Freeze Bridge Controller manages one or more freeze bridges. +The controller can freeze/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +unfreeze/enable the bridges which allows traffic to pass through the +bridge normally. + +Required properties: +- compatible : Should contain "altr,freeze-bridge-controller" +- regs : base address and size for freeze bridge module + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + freeze-controller@100000450 { + compatible = "altr,freeze-bridge-controller"; + regs = <0x1000 0x10>; + bridge-enable = <0>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt new file mode 100644 index 000000000000..6406f9337eeb --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt @@ -0,0 +1,39 @@ +Altera FPGA/HPS Bridge Driver + +Required properties: +- regs : base address and size for AXI bridge module +- compatible : Should contain one of: + "altr,socfpga-lwhps2fpga-bridge", + "altr,socfpga-hps2fpga-bridge", or + "altr,socfpga-fpga2hps-bridge" +- resets : Phandle and reset specifier for this bridge's reset +- clocks : Clocks used by this module. + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup. + 1 if driver should enable bridge at startup. + Default is to leave bridge in its current state. + +Example: + fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + bridge-enable = <0>; + }; + + fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + bridge-enable = <1>; + }; + + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt new file mode 100644 index 000000000000..2fd8e7a84734 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -0,0 +1,19 @@ +Altera SOCFPGA Arria10 FPGA Manager + +Required properties: +- compatible : should contain "altr,socfpga-a10-fpga-mgr" +- reg : base address and size for memory mapped io. + - The first index is for FPGA manager register access. + - The second index is for writing FPGA configuration data. +- resets : Phandle and reset specifier for the device's reset. +- clocks : Clocks used by the device. + +Example: + + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + }; |