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authorFabio Estevam <festevam@denx.de>2023-05-14 14:46:24 +0300
committerNeil Armstrong <neil.armstrong@linaro.org>2023-05-22 16:37:17 +0300
commitec7743c9c48a14aa884d27f2feee1da30810ce0a (patch)
treed5b0af3db9222afa57696f2fc65deed829e602d6 /Documentation/devicetree/bindings/display/bridge
parent0dd53308f74fcb16aa4e5cb90739b831c4a558de (diff)
downloadlinux-ec7743c9c48a14aa884d27f2feee1da30810ce0a.tar.xz
dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'
The Samsung DSIM IP block allows the inversion of the clock and data lanes. Add an optional property called 'lane-polarities' that describes the polarities of the MIPI DSI clock and data lanes. This property is useful for properly describing the hardware when the board designer decided to switch the polarities of the MIPI DSI clock and/or data lanes. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230514114625.98372-1-festevam@gmail.com
Diffstat (limited to 'Documentation/devicetree/bindings/display/bridge')
-rw-r--r--Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml23
1 files changed, 23 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index e841659e20cd..9f61ebdfefa8 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -105,6 +105,29 @@ properties:
DSI output port node to the panel or the next bridge
in the chain.
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+ uniqueItems: true
+ items:
+ enum: [ 1, 2, 3, 4 ]
+
+ lane-polarities:
+ minItems: 1
+ maxItems: 5
+ description:
+ The Samsung MIPI DSI IP requires that all the data lanes have
+ the same polarity.
+
+ dependencies:
+ lane-polarities: [data-lanes]
+
required:
- clock-names
- clocks